SPRS698H November 2010 – March 2020 TMS320F28062 , TMS320F28062F , TMS320F28063 , TMS320F28064 , TMS320F28065 , TMS320F28066 , TMS320F28067 , TMS320F28068F , TMS320F28068M , TMS320F28069 , TMS320F28069F , TMS320F28069M
The devices include two serial communications interface (SCI) modules (SCI-A, SCI-B). The SCI module supports digital communications between the CPU and other asynchronous peripherals that use the standard non-return-to-zero (NRZ) format. The SCI receiver and transmitter are double-buffered, and each has its own separate enable and interrupt bits. Both can be operated independently or simultaneously in the full-duplex mode. To ensure data integrity, the SCI checks received data for break detection, parity, overrun, and framing errors. The bit rate is programmable to over 65000 different speeds through a 16-bit baud-select register.
Features of each SCI module include:
Both pins can be used as GPIO if not used for SCI.
All registers in this module are 8-bit registers that are connected to Peripheral Frame 2. When a register is accessed, the register data is in the lower byte (7–0), and the upper byte (15–8) is read as zeros. Writing to the upper byte has no effect.
|NAME||ADDRESS||SIZE (×16)||EALLOW PROTECTED||DESCRIPTION|
|SCICCRA||0x7050||1||No||SCI-A Communications Control Register|
|SCICTL1A||0x7051||1||No||SCI-A Control Register 1|
|SCIHBAUDA||0x7052||1||No||SCI-A Baud Register, High Bits|
|SCILBAUDA||0x7053||1||No||SCI-A Baud Register, Low Bits|
|SCICTL2A||0x7054||1||No||SCI-A Control Register 2|
|SCIRXSTA||0x7055||1||No||SCI-A Receive Status Register|
|SCIRXEMUA||0x7056||1||No||SCI-A Receive Emulation Data Buffer Register|
|SCIRXBUFA||0x7057||1||No||SCI-A Receive Data Buffer Register|
|SCITXBUFA||0x7059||1||No||SCI-A Transmit Data Buffer Register|
|SCIFFTXA(2)||0x705A||1||No||SCI-A FIFO Transmit Register|
|SCIFFRXA(2)||0x705B||1||No||SCI-A FIFO Receive Register|
|SCIFFCTA(2)||0x705C||1||No||SCI-A FIFO Control Register|
|SCIPRIA||0x705F||1||No||SCI-A Priority Control Register|
|SCICCRB||0x7750||1||SCI-B Communications Control Register|
|SCICTL1B||0x7751||1||SCI-B Control Register 1|
|SCIHBAUDB||0x7752||1||SCI-B Baud Register, High Bits|
|SCILBAUDB||0x7753||1||SCI-B Baud Register, Low Bits|
|SCICTL2B||0x7754||1||SCI-B Control Register 2|
|SCIRXSTB||0x7755||1||SCI-B Receive Status Register|
|SCIRXEMUB||0x7756||1||SCI-B Receive Emulation Data Buffer Register|
|SCIRXBUFB||0x7757||1||SCI-B Receive Data Buffer Register|
|SCITXBUFB||0x7759||1||SCI-B Transmit Data Buffer Register|
|SCIFFTXB(2)||0x775A||1||SCI-B FIFO Transmit Register|
|SCIFFRXB(2)||0x775B||1||SCI-B FIFO Receive Register|
|SCIFFCTB(2)||0x775C||1||SCI-B FIFO Control Register|
|SCIPRIB||0x775F||1||SCI-B Priority Control Register|
Figure 6-37 shows the SCI module block diagram.