SPRS439Q June   2007  – August 2022 TMS320F28232 , TMS320F28232-Q1 , TMS320F28234 , TMS320F28234-Q1 , TMS320F28235 , TMS320F28235-Q1 , TMS320F28332 , TMS320F28333 , TMS320F28334 , TMS320F28335 , TMS320F28335-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1. 3.1 Functional Block Diagram
  4. 4 Revision History
  5. 5 Device Comparison
    1. 5.1 Related Products
  6. 6 Terminal Configuration and Functions
    1. 6.1 Pin Diagrams
    2. 6.2 Signal Descriptions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings – Automotive
    3. 7.3  ESD Ratings – Commercial
    4. 7.4  Recommended Operating Conditions
    5. 7.5  Power Consumption Summary
      1. 7.5.1 TMS320F28335/F28235 Current Consumption by Power-Supply Pins at 150-MHz SYSCLKOUT
      2. 7.5.2 TMS320F28334/F28234 Current Consumption by Power-Supply Pins at 150-MHz SYSCLKOUT
      3. 7.5.3 Reducing Current Consumption
      4. 7.5.4 Current Consumption Graphs
    6. 7.6  Electrical Characteristics
    7. 7.7  Thermal Resistance Characteristics
      1. 7.7.1 PGF Package
      2. 7.7.2 PTP Package
      3. 7.7.3 ZHH Package
      4. 7.7.4 ZAY Package
      5. 7.7.5 ZJZ Package
    8. 7.8  Thermal Design Considerations
    9. 7.9  Timing and Switching Characteristics
      1. 7.9.1 Timing Parameter Symbology
        1. 7.9.1.1 General Notes on Timing Parameters
        2. 7.9.1.2 Test Load Circuit
        3. 7.9.1.3 Device Clock Table
          1. 7.9.1.3.1 Clocking and Nomenclature (150-MHz Devices)
          2. 7.9.1.3.2 Clocking and Nomenclature (100-MHz Devices)
      2. 7.9.2 Power Sequencing
        1. 7.9.2.1 Power Management and Supervisory Circuit Solutions
        2. 7.9.2.2 Reset (XRS) Timing Requirements
      3. 7.9.3 Clock Requirements and Characteristics
        1. 7.9.3.1 Input Clock Frequency
        2. 7.9.3.2 XCLKIN Timing Requirements – PLL Enabled
        3. 7.9.3.3 XCLKIN Timing Requirements – PLL Disabled
        4. 7.9.3.4 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)
        5. 7.9.3.5 Timing Diagram
      4. 7.9.4 Peripherals
        1. 7.9.4.1 General-Purpose Input/Output (GPIO)
          1. 7.9.4.1.1 GPIO - Output Timing
            1. 7.9.4.1.1.1 General-Purpose Output Switching Characteristics
          2. 7.9.4.1.2 GPIO - Input Timing
            1. 7.9.4.1.2.1 General-Purpose Input Timing Requirements
          3. 7.9.4.1.3 Sampling Window Width for Input Signals
          4. 7.9.4.1.4 Low-Power Mode Wakeup Timing
            1. 7.9.4.1.4.1 IDLE Mode Timing Requirements
            2. 7.9.4.1.4.2 IDLE Mode Switching Characteristics
            3. 7.9.4.1.4.3 IDLE Mode Timing Diagram
            4. 7.9.4.1.4.4 STANDBY Mode Timing Requirements
            5. 7.9.4.1.4.5 STANDBY Mode Switching Characteristics
            6. 7.9.4.1.4.6 STANDBY Mode Timing Diagram
            7. 7.9.4.1.4.7 HALT Mode Timing Requirements
            8. 7.9.4.1.4.8 HALT Mode Switching Characteristics
            9. 7.9.4.1.4.9 HALT Mode Timing Diagram
        2. 7.9.4.2 Enhanced Control Peripherals
          1. 7.9.4.2.1 Enhanced Pulse Width Modulator (ePWM) Timing
            1. 7.9.4.2.1.1 ePWM Timing Requirements
            2. 7.9.4.2.1.2 ePWM Switching Characteristics
          2. 7.9.4.2.2 Trip-Zone Input Timing
            1. 7.9.4.2.2.1 Trip-Zone Input Timing Requirements
          3. 7.9.4.2.3 High-Resolution PWM Timing
            1. 7.9.4.2.3.1 High-Resolution PWM Characteristics at SYSCLKOUT = (60–150 MHz)
          4. 7.9.4.2.4 Enhanced Capture (eCAP) Timing
            1. 7.9.4.2.4.1 Enhanced Capture (eCAP) Timing Requirements
            2. 7.9.4.2.4.2 eCAP Switching Characteristics
          5. 7.9.4.2.5 Enhanced Quadrature Encoder Pulse (eQEP) Timing
            1. 7.9.4.2.5.1 Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements
            2. 7.9.4.2.5.2 eQEP Switching Characteristics
          6. 7.9.4.2.6 ADC Start-of-Conversion Timing
            1. 7.9.4.2.6.1 External ADC Start-of-Conversion Switching Characteristics
            2. 7.9.4.2.6.2 ADCSOCAO or ADCSOCBO Timing
        3. 7.9.4.3 External Interrupt Timing
          1. 7.9.4.3.1 External Interrupt Timing Requirements
          2. 7.9.4.3.2 External Interrupt Switching Characteristics
          3. 7.9.4.3.3 External Interrupt Timing Diagram
        4. 7.9.4.4 I2C Electrical Specification and Timing
          1. 7.9.4.4.1 I2C Timing
        5. 7.9.4.5 Serial Peripheral Interface (SPI) Timing
          1. 7.9.4.5.1 Master Mode Timing
            1. 7.9.4.5.1.1 SPI Master Mode External Timing (Clock Phase = 0)
            2. 7.9.4.5.1.2 SPI Master Mode External Timing (Clock Phase = 1)
          2. 7.9.4.5.2 Slave Mode Timing
            1. 7.9.4.5.2.1 SPI Slave Mode External Timing (Clock Phase = 0)
            2. 7.9.4.5.2.2 SPI Slave Mode External Timing (Clock Phase = 1)
        6. 7.9.4.6 Multichannel Buffered Serial Port (McBSP) Timing
          1. 7.9.4.6.1 McBSP Transmit and Receive Timing
            1. 7.9.4.6.1.1 McBSP Timing Requirements
            2. 7.9.4.6.1.2 McBSP Switching Characteristics
          2. 7.9.4.6.2 McBSP as SPI Master or Slave Timing
            1. 7.9.4.6.2.1 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)
            2. 7.9.4.6.2.2 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)
            3. 7.9.4.6.2.3 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)
            4. 7.9.4.6.2.4 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)
            5. 7.9.4.6.2.5 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)
            6. 7.9.4.6.2.6 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)
            7. 7.9.4.6.2.7 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1)
            8. 7.9.4.6.2.8 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1)
      5. 7.9.5 JTAG Debug Probe Connection Without Signal Buffering for the MCU
      6. 7.9.6 External Interface (XINTF) Timing
        1. 7.9.6.1 USEREADY = 0
        2. 7.9.6.2 Synchronous Mode (USEREADY = 1, READYMODE = 0)
        3. 7.9.6.3 Asynchronous Mode (USEREADY = 1, READYMODE = 1)
        4. 7.9.6.4 XINTF Signal Alignment to XCLKOUT
        5. 7.9.6.5 External Interface Read Timing
          1. 7.9.6.5.1 External Interface Read Timing Requirements
          2. 7.9.6.5.2 External Interface Read Switching Characteristics
        6. 7.9.6.6 External Interface Write Timing
          1. 7.9.6.6.1 External Interface Write Switching Characteristics
        7. 7.9.6.7 External Interface Ready-on-Read Timing With One External Wait State
          1. 7.9.6.7.1 External Interface Read Switching Characteristics (Ready-on-Read, One Wait State)
          2. 7.9.6.7.2 External Interface Read Timing Requirements (Ready-on-Read, One Wait State)
          3. 7.9.6.7.3 Synchronous XREADY Timing Requirements (Ready-on-Read, One Wait State)
          4. 7.9.6.7.4 Asynchronous XREADY Timing Requirements (Ready-on-Read, One Wait State)
        8. 7.9.6.8 External Interface Ready-on-Write Timing With One External Wait State
          1. 7.9.6.8.1 External Interface Write Switching Characteristics (Ready-on-Write, One Wait State)
          2. 7.9.6.8.2 Synchronous XREADY Timing Requirements (Ready-on-Write, One Wait State)
          3. 7.9.6.8.3 Asynchronous XREADY Timing Requirements (Ready-on-Write, One Wait State)
        9. 7.9.6.9 XHOLD and XHOLDA Timing
          1. 7.9.6.9.1 XHOLD/ XHOLDA Timing Requirements (XCLKOUT = XTIMCLK)
          2. 7.9.6.9.2 XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK)
      7. 7.9.7 Flash Timing
        1. 7.9.7.1 Flash Endurance for A and S Temperature Material
        2. 7.9.7.2 Flash Endurance for Q Temperature Material
        3. 7.9.7.3 Flash Parameters at 150-MHz SYSCLKOUT
        4. 7.9.7.4 Flash/OTP Access Timing
        5. 7.9.7.5 Flash Data Retention Duration
    10. 7.10 On-Chip Analog-to-Digital Converter
      1. 7.10.1 ADC Electrical Characteristics (over recommended operating conditions)
      2. 7.10.2 ADC Power-Up Control Bit Timing
        1. 7.10.2.1 ADC Power-Up Delays
        2. 7.10.2.2 Typical Current Consumption for Different ADC Configurations (at 25-MHz ADCCLK)
      3. 7.10.3 Definitions
      4. 7.10.4 Sequential Sampling Mode (Single-Channel) (SMODE = 0)
        1. 7.10.4.1 Sequential Sampling Mode Timing
      5. 7.10.5 Simultaneous Sampling Mode (Dual-Channel) (SMODE = 1)
        1. 7.10.5.1 Simultaneous Sampling Mode Timing
      6. 7.10.6 Detailed Descriptions
    11. 7.11 Migrating Between F2833x Devices and F2823x Devices
  8. 8 Detailed Description
    1. 8.1 Brief Descriptions
      1. 8.1.1  C28x CPU
      2. 8.1.2  Memory Bus (Harvard Bus Architecture)
      3. 8.1.3  Peripheral Bus
      4. 8.1.4  Real-Time JTAG and Analysis
      5. 8.1.5  External Interface (XINTF)
      6. 8.1.6  Flash
      7. 8.1.7  M0, M1 SARAMs
      8. 8.1.8  L0, L1, L2, L3, L4, L5, L6, L7 SARAMs
      9. 8.1.9  Boot ROM
        1. 8.1.9.1 Peripheral Pins Used by the Bootloader
      10. 8.1.10 Security
      11. 8.1.11 Peripheral Interrupt Expansion (PIE) Block
      12. 8.1.12 External Interrupts (XINT1–XINT7, XNMI)
      13. 8.1.13 Oscillator and PLL
      14. 8.1.14 Watchdog
      15. 8.1.15 Peripheral Clocking
      16. 8.1.16 Low-Power Modes
      17. 8.1.17 Peripheral Frames 0, 1, 2, 3 (PFn)
      18. 8.1.18 General-Purpose Input/Output (GPIO) Multiplexer
      19. 8.1.19 32-Bit CPU-Timers (0, 1, 2)
      20. 8.1.20 Control Peripherals
      21. 8.1.21 Serial Port Peripherals
    2. 8.2 Peripherals
      1. 8.2.1  DMA Overview
      2. 8.2.2  32-Bit CPU-Timer 0, CPU-Timer 1, CPU-Timer 2
      3. 8.2.3  Enhanced PWM Modules
      4. 8.2.4  High-Resolution PWM (HRPWM)
      5. 8.2.5  Enhanced CAP Modules
      6. 8.2.6  Enhanced QEP Modules
      7. 8.2.7  Analog-to-Digital Converter (ADC) Module
        1. 8.2.7.1 ADC Connections if the ADC Is Not Used
        2. 8.2.7.2 ADC Registers
        3. 8.2.7.3 ADC Calibration
      8. 8.2.8  Multichannel Buffered Serial Port (McBSP) Module
      9. 8.2.9  Enhanced Controller Area Network (eCAN) Modules (eCAN-A and eCAN-B)
      10. 8.2.10 Serial Communications Interface (SCI) Modules (SCI-A, SCI-B, SCI-C)
      11. 8.2.11 Serial Peripheral Interface (SPI) Module (SPI-A)
      12. 8.2.12 Inter-Integrated Circuit (I2C)
      13. 8.2.13 GPIO MUX
      14. 8.2.14 External Interface (XINTF)
    3. 8.3 Memory Maps
    4. 8.4 Register Map
      1. 8.4.1 Device Emulation Registers
    5. 8.5 Interrupts
      1. 8.5.1 External Interrupts
    6. 8.6 System Control
      1. 8.6.1 OSC and PLL Block
        1. 8.6.1.1 External Reference Oscillator Clock Option
        2. 8.6.1.2 PLL-Based Clock Module
        3. 8.6.1.3 Loss of Input Clock
      2. 8.6.2 Watchdog Block
    7. 8.7 Low-Power Modes Block
  9. 9 Applications, Implementation, and Layout
    1. 9.1 TI Reference Design
  10. 10Device and Documentation Support
    1. 10.1 Getting Started and Next Steps
    2. 10.2 Device and Development Support Tool Nomenclature
    3. 10.3 Tools and Software
    4. 10.4 Documentation Support
    5. 10.5 Support Resources
    6. 10.6 Trademarks
    7. 10.7 Electrostatic Discharge Caution
    8. 10.8 Glossary
  11. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Package Redesign Details
    2. 11.2 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PGF|176
  • PTP|176
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.10 Serial Communications Interface (SCI) Modules (SCI-A, SCI-B, SCI-C)

The devices include three serial communications interface (SCI) modules. The SCI modules support digital communications between the CPU and other asynchronous peripherals that use the standard nonreturn-to-zero (NRZ) format. The SCI receiver and transmitter are double-buffered, and each has its own separate enable and interrupt bits. Both can be operated independently or simultaneously in the full-duplex mode. To ensure data integrity, the SCI checks received data for break detection, parity, overrun, and framing errors. The bit rate is programmable to more than 65000 different speeds through a 16-bit baud-select register.

Features of each SCI module include:

  • Two external pins:
    • SCITXD: SCI transmit-output pin
    • SCIRXD: SCI receive-input pin
      Note: Both pins can be used as GPIO if not used for SCI.
    • Baud rate programmable to 64K different rates:
    GUID-B3E1DF2B-6AE6-4F53-9BC3-8260633DEFD3-low.gif
    Note:

    See Section 7 for maximum I/O pin toggling speed.

  • Data-word format
    • One start bit
    • Data-word length programmable from one to eight bits
    • Optional even/odd/no parity bit
    • One or two stop bits
  • Four error-detection flags: parity, overrun, framing, and break detection
  • Two wake-up multiprocessor modes: idle-line and address bit
  • Half- or full-duplex operation
  • Double-buffered receive and transmit functions
  • Transmitter and receiver operations can be accomplished through interrupt-driven or polled algorithms with status flags.
    • Transmitter: TXRDY flag (transmitter-buffer register is ready to receive another character) and TX EMPTY flag (transmitter-shift register is empty)
    • Receiver: RXRDY flag (receiver-buffer register is ready to receive another character), BRKDT flag (break condition occurred), and RX ERROR flag (monitoring four interrupt conditions)
  • Separate enable bits for transmitter and receiver interrupts (except BRKDT)
  • NRZ (nonreturn-to-zero) format
Note:

All registers in this module are 8-bit registers that are connected to Peripheral Frame 2. When a register is accessed, the register data is in the lower byte (7-0), and the upper byte (15-8) is read as zeros. Writing to the upper byte has no effect.

Enhanced features:

  • Auto baud-detect hardware logic
  • 16-level transmit/receive FIFO

The SCI port operation is configured and controlled by the registers listed in Table 8-12, Table 8-13, and Table 8-14.

Table 8-12 SCI-A Registers
NAME(1) ADDRESS SIZE (x16) DESCRIPTION
SCICCRA 0x7050 1 SCI-A Communications Control Register
SCICTL1A 0x7051 1 SCI-A Control Register 1
SCIHBAUDA 0x7052 1 SCI-A Baud Register, High Bits
SCILBAUDA 0x7053 1 SCI-A Baud Register, Low Bits
SCICTL2A 0x7054 1 SCI-A Control Register 2
SCIRXSTA 0x7055 1 SCI-A Receive Status Register
SCIRXEMUA 0x7056 1 SCI-A Receive Emulation Data Buffer Register
SCIRXBUFA 0x7057 1 SCI-A Receive Data Buffer Register
SCITXBUFA 0x7059 1 SCI-A Transmit Data Buffer Register
SCIFFTXA(2) 0x705A 1 SCI-A FIFO Transmit Register
SCIFFRXA(2) 0x705B 1 SCI-A FIFO Receive Register
SCIFFCTA(2) 0x705C 1 SCI-A FIFO Control Register
SCIPRIA 0x705F 1 SCI-A Priority Control Register
(1) Registers in this table are mapped to Peripheral Frame 2 space. This space only allows 16-bit accesses. 32-bit accesses produce undefined results.
(2) These registers are new registers for the FIFO mode.
Table 8-13 SCI-B Registers
NAME(1) ADDRESS SIZE (x16) DESCRIPTION
SCICCRB 0x7750 1 SCI-B Communications Control Register
SCICTL1B 0x7751 1 SCI-B Control Register 1
SCIHBAUDB 0x7752 1 SCI-B Baud Register, High Bits
SCILBAUDB 0x7753 1 SCI-B Baud Register, Low Bits
SCICTL2B 0x7754 1 SCI-B Control Register 2
SCIRXSTB 0x7755 1 SCI-B Receive Status Register
SCIRXEMUB 0x7756 1 SCI-B Receive Emulation Data Buffer Register
SCIRXBUFB 0x7757 1 SCI-B Receive Data Buffer Register
SCITXBUFB 0x7759 1 SCI-B Transmit Data Buffer Register
SCIFFTXB(2) 0x775A 1 SCI-B FIFO Transmit Register
SCIFFRXB(2) 0x775B 1 SCI-B FIFO Receive Register
SCIFFCTB(2) 0x775C 1 SCI-B FIFO Control Register
SCIPRIB 0x775F 1 SCI-B Priority Control Register
(1) Registers in this table are mapped to Peripheral Frame 2 space. This space only allows 16-bit accesses. 32-bit accesses produce undefined results.
(2) These registers are new registers for the FIFO mode.
Table 8-14 SCI-C Registers
NAME(1) ADDRESS SIZE (x16) DESCRIPTION
SCICCRC 0x7770 1 SCI-C Communications Control Register
SCICTL1C 0x7771 1 SCI-C Control Register 1
SCIHBAUDC 0x7772 1 SCI-C Baud Register, High Bits
SCILBAUDC 0x7773 1 SCI-C Baud Register, Low Bits
SCICTL2C 0x7774 1 SCI-C Control Register 2
SCIRXSTC 0x7775 1 SCI-C Receive Status Register
SCIRXEMUC 0x7776 1 SCI-C Receive Emulation Data Buffer Register
SCIRXBUFC 0x7777 1 SCI-C Receive Data Buffer Register
SCITXBUFC 0x7779 1 SCI-C Transmit Data Buffer Register
SCIFFTXC(2) 0x777A 1 SCI-C FIFO Transmit Register
SCIFFRXC(2) 0x777B 1 SCI-C FIFO Receive Register
SCIFFCTC(2) 0x777C 1 SCI-C FIFO Control Register
SCIPRC 0x777F 1 SCI-C Priority Control Register
(1) Registers in this table are mapped to Peripheral Frame 2 space. This space only allows 16-bit accesses. 32-bit accesses produce undefined results.
(2) These registers are new registers for the FIFO mode.

Figure 8-15 shows the SCI module block diagram.

GUID-44AFDE94-DD95-4C1C-ADBF-E13F50D53FE2-low.gif Figure 8-15 Serial Communications Interface (SCI) Module Block Diagram