Refer to the PDF data sheet for device specific package drawings
The devices support eight masked external interrupts (XINT1–XINT7, XNMI). XNMI can be connected to the INT13 or NMI interrupt of the CPU. Each of the interrupts can be selected for negative, positive, or both negative and positive edge triggering and can also be enabled or disabled (including the XNMI). XINT1, XINT2, and XNMI also contain a 16-bit free-running up counter, which is reset to zero when a valid interrupt edge is detected. This counter can be used to accurately time-stamp the interrupt. Unlike the 281x devices, there are no dedicated pins for the external interrupts. XINT1 XINT2, and XNMI interrupts can accept inputs from GPIO0–GPIO31 pins. XINT3–XINT7 interrupts can accept inputs from GPIO32–GPIO63 pins.