Refer to the PDF data sheet for device specific package drawings
No requirements are placed on the power-up and power-down sequences of the various power pins to ensure the correct reset state for all the modules. However, if the 3.3-V transistors in the level shifting output buffers of the I/O pins are powered prior to the 1.9-V/1.8-V transistors, it is possible for the output buffers to turn on, causing a glitch to occur on the pin during power up. To avoid this behavior, power the VDD pins prior to or simultaneously with the VDDIO pins, ensuring that the VDD pins have reached 0.7 V before the VDDIO pins reach 0.7 V.
There are some requirements on the XRS pin:
No voltage larger than a diode drop (0.7 V) above VDDIO should be applied to any digital pin (for analog pins, this value is 0.7 V above VDDA) before powering up the device. Furthermore, VDDIO and VDDA should always be within 0.3 V of each other. Voltages applied to pins on an unpowered device can bias internal P-N junctions in unintended ways and produce unpredictable results.