SPRS439O June   2007  – April 2019 TMS320F28232 , TMS320F28234 , TMS320F28235 , TMS320F28332 , TMS320F28333 , TMS320F28334 , TMS320F28335

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings – Automotive
    3. 5.3  ESD Ratings – Commercial
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Power Consumption Summary
      1. Table 5-1 TMS320F28335/F28235 Current Consumption by Power-Supply Pins at 150-MHz SYSCLKOUT
      2. Table 5-2 TMS320F28334/F28234 Current Consumption by Power-Supply Pins at 150-MHz SYSCLKOUT
      3. 5.5.1     Reducing Current Consumption
      4. 5.5.2     Current Consumption Graphs
    6. 5.6  Electrical Characteristics
    7. 5.7  Thermal Resistance Characteristics
      1. 5.7.1 PGF Package
      2. 5.7.2 PTP Package
      3. 5.7.3 ZHH Package
      4. 5.7.4 ZJZ Package
    8. 5.8  Thermal Design Considerations
    9. 5.9  Timing and Switching Characteristics
      1. 5.9.1 Timing Parameter Symbology
        1. 5.9.1.1 General Notes on Timing Parameters
        2. 5.9.1.2 Test Load Circuit
        3. 5.9.1.3 Device Clock Table
          1. Table 5-4 Clocking and Nomenclature (150-MHz Devices)
          2. Table 5-5 Clocking and Nomenclature (100-MHz Devices)
      2. 5.9.2 Power Sequencing
        1. 5.9.2.1   Power Management and Supervisory Circuit Solutions
        2. Table 5-6 Reset (XRS) Timing Requirements
      3. 5.9.3 Clock Requirements and Characteristics
        1. Table 5-7  Input Clock Frequency
        2. Table 5-8  XCLKIN Timing Requirements – PLL Enabled
        3. Table 5-9  XCLKIN Timing Requirements – PLL Disabled
        4. Table 5-10 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)
      4. 5.9.4 Peripherals
        1. 5.9.4.1 General-Purpose Input/Output (GPIO)
          1. 5.9.4.1.1 GPIO - Output Timing
            1. Table 5-11 General-Purpose Output Switching Characteristics
          2. 5.9.4.1.2 GPIO - Input Timing
            1. Table 5-12 General-Purpose Input Timing Requirements
          3. 5.9.4.1.3 Sampling Window Width for Input Signals
          4. 5.9.4.1.4 Low-Power Mode Wakeup Timing
            1. Table 5-13 IDLE Mode Timing Requirements
            2. Table 5-14 IDLE Mode Switching Characteristics
            3. Table 5-15 STANDBY Mode Timing Requirements
            4. Table 5-16 STANDBY Mode Switching Characteristics
            5. Table 5-17 HALT Mode Timing Requirements
            6. Table 5-18 HALT Mode Switching Characteristics
        2. 5.9.4.2 Enhanced Control Peripherals
          1. 5.9.4.2.1 Enhanced Pulse Width Modulator (ePWM) Timing
            1. Table 5-19 ePWM Timing Requirements
            2. Table 5-20 ePWM Switching Characteristics
          2. 5.9.4.2.2 Trip-Zone Input Timing
            1. Table 5-21 Trip-Zone Input Timing Requirements
          3. 5.9.4.2.3 High-Resolution PWM Timing
            1. Table 5-22 High-Resolution PWM Characteristics at SYSCLKOUT = (60–150 MHz)
          4. 5.9.4.2.4 Enhanced Capture (eCAP) Timing
            1. Table 5-23 Enhanced Capture (eCAP) Timing Requirements
            2. Table 5-24 eCAP Switching Characteristics
          5. 5.9.4.2.5 Enhanced Quadrature Encoder Pulse (eQEP) Timing
            1. Table 5-25 Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements
            2. Table 5-26 eQEP Switching Characteristics
          6. 5.9.4.2.6 ADC Start-of-Conversion Timing
            1. Table 5-27 External ADC Start-of-Conversion Switching Characteristics
        3. 5.9.4.3 External Interrupt Timing
          1. Table 5-28 External Interrupt Timing Requirements
          2. Table 5-29 External Interrupt Switching Characteristics
        4. 5.9.4.4 I2C Electrical Specification and Timing
          1. Table 5-30 I2C Timing
        5. 5.9.4.5 Serial Peripheral Interface (SPI) Timing
          1. 5.9.4.5.1 Master Mode Timing
            1. Table 5-31 SPI Master Mode External Timing (Clock Phase = 0)
            2. Table 5-32 SPI Master Mode External Timing (Clock Phase = 1)
          2. 5.9.4.5.2 Slave Mode Timing
            1. Table 5-33 SPI Slave Mode External Timing (Clock Phase = 0)
            2. Table 5-34 SPI Slave Mode External Timing (Clock Phase = 1)
        6. 5.9.4.6 Multichannel Buffered Serial Port (McBSP) Timing
          1. 5.9.4.6.1 McBSP Transmit and Receive Timing
            1. Table 5-35 McBSP Timing Requirements
            2. Table 5-36 McBSP Switching Characteristics
          2. 5.9.4.6.2 McBSP as SPI Master or Slave Timing
            1. Table 5-37 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)
            2. Table 5-38 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)
            3. Table 5-39 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)
            4. Table 5-40 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)
            5. Table 5-41 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)
            6. Table 5-42 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)
            7. Table 5-43 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1)
            8. Table 5-44 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1)
      5. 5.9.5 Emulator Connection Without Signal Buffering for the DSP
      6. 5.9.6 External Interface (XINTF) Timing
        1. 5.9.6.1 USEREADY = 0
        2. 5.9.6.2 Synchronous Mode (USEREADY = 1, READYMODE = 0)
        3. 5.9.6.3 Asynchronous Mode (USEREADY = 1, READYMODE = 1)
        4. 5.9.6.4 XINTF Signal Alignment to XCLKOUT
        5. 5.9.6.5 External Interface Read Timing
          1. Table 5-47 External Interface Read Timing Requirements
          2. Table 5-48 External Interface Read Switching Characteristics
        6. 5.9.6.6 External Interface Write Timing
          1. Table 5-49 External Interface Write Switching Characteristics
        7. 5.9.6.7 External Interface Ready-on-Read Timing With One External Wait State
          1. Table 5-50 External Interface Read Switching Characteristics (Ready-on-Read, One Wait State)
          2. Table 5-51 External Interface Read Timing Requirements (Ready-on-Read, One Wait State)
          3. Table 5-52 Synchronous XREADY Timing Requirements (Ready-on-Read, One Wait State)
          4. Table 5-53 Asynchronous XREADY Timing Requirements (Ready-on-Read, One Wait State)
        8. 5.9.6.8 External Interface Ready-on-Write Timing With One External Wait State
          1. Table 5-54 External Interface Write Switching Characteristics (Ready-on-Write, One Wait State)
          2. Table 5-55 Synchronous XREADY Timing Requirements (Ready-on-Write, One Wait State)
          3. Table 5-56 Asynchronous XREADY Timing Requirements (Ready-on-Write, One Wait State)
        9. 5.9.6.9 XHOLD and XHOLDA Timing
          1. Table 5-57 XHOLD/XHOLDA Timing Requirements (XCLKOUT = XTIMCLK)
          2. Table 5-58 XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK)
      7. 5.9.7 Flash Timing
        1. Table 5-59 Flash Endurance for A and S Temperature Material
        2. Table 5-60 Flash Endurance for Q Temperature Material
        3. Table 5-61 Flash Parameters at 150-MHz SYSCLKOUT
        4. Table 5-62 Flash/OTP Access Timing
        5. Table 5-63 Flash Data Retention Duration
    10. 5.10 On-Chip Analog-to-Digital Converter
      1. Table 5-65 ADC Electrical Characteristics (over recommended operating conditions)
      2. 5.10.1     ADC Power-Up Control Bit Timing
        1. Table 5-66 ADC Power-Up Delays
        2. Table 5-67 Typical Current Consumption for Different ADC Configurations (at 25-MHz ADCCLK)
      3. 5.10.2     Definitions
      4. 5.10.3     Sequential Sampling Mode (Single-Channel) (SMODE = 0)
        1. Table 5-68 Sequential Sampling Mode Timing
      5. 5.10.4     Simultaneous Sampling Mode (Dual-Channel) (SMODE = 1)
        1. Table 5-69 Simultaneous Sampling Mode Timing
      6. 5.10.5     Detailed Descriptions
    11. 5.11 Migrating Between F2833x Devices and F2823x Devices
  6. 6Detailed Description
    1. 6.1 Brief Descriptions
      1. 6.1.1  C28x CPU
      2. 6.1.2  Memory Bus (Harvard Bus Architecture)
      3. 6.1.3  Peripheral Bus
      4. 6.1.4  Real-Time JTAG and Analysis
      5. 6.1.5  External Interface (XINTF)
      6. 6.1.6  Flash
      7. 6.1.7  M0, M1 SARAMs
      8. 6.1.8  L0, L1, L2, L3, L4, L5, L6, L7 SARAMs
      9. 6.1.9  Boot ROM
        1. 6.1.9.1 Peripheral Pins Used by the Bootloader
      10. 6.1.10 Security
      11. 6.1.11 Peripheral Interrupt Expansion (PIE) Block
      12. 6.1.12 External Interrupts (XINT1–XINT7, XNMI)
      13. 6.1.13 Oscillator and PLL
      14. 6.1.14 Watchdog
      15. 6.1.15 Peripheral Clocking
      16. 6.1.16 Low-Power Modes
      17. 6.1.17 Peripheral Frames 0, 1, 2, 3 (PFn)
      18. 6.1.18 General-Purpose Input/Output (GPIO) Multiplexer
      19. 6.1.19 32-Bit CPU-Timers (0, 1, 2)
      20. 6.1.20 Control Peripherals
      21. 6.1.21 Serial Port Peripherals
    2. 6.2 Peripherals
      1. 6.2.1  DMA Overview
      2. 6.2.2  32-Bit CPU-Timer 0, CPU-Timer 1, CPU-Timer 2
      3. 6.2.3  Enhanced PWM Modules
      4. 6.2.4  High-Resolution PWM (HRPWM)
      5. 6.2.5  Enhanced CAP Modules
      6. 6.2.6  Enhanced QEP Modules
      7. 6.2.7  Analog-to-Digital Converter (ADC) Module
        1. 6.2.7.1 ADC Connections if the ADC Is Not Used
        2. 6.2.7.2 ADC Registers
        3. 6.2.7.3 ADC Calibration
      8. 6.2.8  Multichannel Buffered Serial Port (McBSP) Module
      9. 6.2.9  Enhanced Controller Area Network (eCAN) Modules (eCAN-A and eCAN-B)
      10. 6.2.10 Serial Communications Interface (SCI) Modules (SCI-A, SCI-B, SCI-C)
      11. 6.2.11 Serial Peripheral Interface (SPI) Module (SPI-A)
      12. 6.2.12 Inter-Integrated Circuit (I2C)
      13. 6.2.13 GPIO MUX
      14. 6.2.14 External Interface (XINTF)
    3. 6.3 Memory Maps
    4. 6.4 Register Map
      1. 6.4.1 Device Emulation Registers
    5. 6.5 Interrupts
      1. 6.5.1 External Interrupts
    6. 6.6 System Control
      1. 6.6.1 OSC and PLL Block
        1. 6.6.1.1 External Reference Oscillator Clock Option
        2. 6.6.1.2 PLL-Based Clock Module
        3. 6.6.1.3 Loss of Input Clock
      2. 6.6.2 Watchdog Block
    7. 6.7 Low-Power Modes Block
  7. 7Applications, Implementation, and Layout
    1. 7.1 TI Design or Reference Design
  8. 8Device and Documentation Support
    1. 8.1 Getting Started
    2. 8.2 Device and Development Support Tool Nomenclature
    3. 8.3 Tools and Software
    4. 8.4 Documentation Support
    5. 8.5 Related Links
    6. 8.6 Community Resources
    7. 8.7 Trademarks
    8. 8.8 Electrostatic Discharge Caution
    9. 8.9 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PGF|176
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Signal Descriptions

Table 4-1 describes the signals. The GPIO function (shown in Italics) is the default at reset. The peripheral signals that are listed under them are alternate functions. Some peripheral functions may not be available in all devices. See Table 3-1 and Table 3-2 for details. Inputs are not 5-V tolerant. All pins capable of producing an XINTF output function have a drive strength of 8 mA (typical). This is true even if the pin is not configured for XINTF functionality. All other pins have a drive strength of 4-mA drive typical (unless otherwise indicated). All GPIO pins are I/O/Z and have an internal pullup, which can be selectively enabled or disabled on a per-pin basis. This feature only applies to the GPIO pins. The pullups on GPIO0–GPIO11 pins are not enabled at reset. The pullups on GPIO12–GPIO87 are enabled upon reset.

Table 4-1 Signal Descriptions

NAME PIN NO. DESCRIPTION (1)
PGF,
PTP
PIN #
ZHH
BALL #
ZJZ
BALL #
JTAG
TRST 78 M10 L11 JTAG test reset with internal pulldown. TRST, when driven high, gives the scan system control of the operations of the device. If this signal is not connected or driven low, the device operates in its functional mode, and the test reset signals are ignored.
NOTE: TRST is an active high test pin and must be maintained low at all times during normal device operation. An external pulldown resistor is required on this pin. The value of this resistor should be based on drive strength of the debugger pods applicable to the design. A 2.2-kΩ resistor generally offers adequate protection. Because this is application-specific, TI recommends validating each target board for proper operation of the debugger and the application. (I, ↓)
TCK 87 N12 M14 JTAG test clock with internal pullup (I, ↑)
TMS 79 P10 M12 JTAG test-mode select (TMS) with internal pullup. This serial control input is clocked into the TAP controller on the rising edge of TCK. (I, ↑)
TDI 76 M9 N12 JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected register (instruction or data) on a rising edge of TCK. (I, ↑)
TDO 77 K9 N13 JTAG scan out, test data output (TDO). The contents of the selected register (instruction or data) are shifted out of TDO on the falling edge of TCK. (O/Z 8 mA drive)
EMU0 85 L11 N7 Emulator pin 0. When TRST is driven high, this pin is used as an interrupt to or from the emulator system and is defined as input/output through the JTAG scan. This pin is also used to put the device into boundary-scan mode. With the EMU0 pin at a logic-high state and the EMU1 pin at a logic-low state, a rising edge on the TRST pin would latch the device into boundary-scan mode. (I/O/Z, 8 mA drive ↑)
NOTE: An external pullup resistor is required on this pin. The value of this resistor should be based on the drive strength of the debugger pods applicable to the design. A 2.2-kΩ to 4.7-kΩ resistor is generally adequate. Because this is application-specific, TI recommends validating each target board for proper operation of the debugger and the application.
EMU1 86 P12 P8 Emulator pin 1. When TRST is driven high, this pin is used as an interrupt to or from the emulator system and is defined as input/output through the JTAG scan. This pin is also used to put the device into boundary-scan mode. With the EMU0 pin at a logic-high state and the EMU1 pin at a logic-low state, a rising edge on the TRST pin would latch the device into boundary-scan mode. (I/O/Z, 8 mA drive ↑)
NOTE: An external pullup resistor is required on this pin. The value of this resistor should be based on the drive strength of the debugger pods applicable to the design. A 2.2-kΩ to 4.7-kΩ resistor is generally adequate. Because this is application-specific, TI recommends validating each target board for proper operation of the debugger and the application.
FLASH
VDD3VFL 84 M11 L9 3.3-V Flash Core Power Pin. This pin should be connected to 3.3 V at all times.
TEST1 81 K10 M7 Test Pin. Reserved for TI. Must be left unconnected. (I/O)
TEST2 82 P11 L7 Test Pin. Reserved for TI. Must be left unconnected. (I/O)
CLOCK
XCLKOUT 138 C11 A10 Output clock derived from SYSCLKOUT. XCLKOUT is either the same frequency, one-half the frequency, or one-fourth the frequency of SYSCLKOUT. This is controlled by bits 18:16 (XTIMCLK) and bit 2 (CLKMODE) in the XINTCNF2 register. At reset, XCLKOUT = SYSCLKOUT/4. The XCLKOUT signal can be turned off by setting XINTCNF2[CLKOFF] to 1. Unlike other GPIO pins, the XCLKOUT pin is not placed in high-impedance state during a reset. (O/Z, 8 mA drive).
XCLKIN 105 J14 G13 External Oscillator Input. This pin is to feed a clock from an external 3.3-V oscillator. In this case, the X1 pin must be tied to GND. If a crystal/resonator is used (or if an external 1.9-V oscillator is used to feed clock to X1 pin), this pin must be tied to GND. (I)
X1 104 J13 G14 Internal/External Oscillator Input. To use the internal oscillator, a quartz crystal or a ceramic resonator may be connected across X1 and X2. The X1 pin is referenced to the 1.9-V/1.8-V core digital power supply. A 1.9-V/1.8-V external oscillator may be connected to the X1 pin. In this case, the XCLKIN pin must be connected to ground. If a 3.3-V external oscillator is used with the XCLKIN pin, X1 must be tied to GND. (I)
X2 102 J11 H14 Internal Oscillator Output. A quartz crystal or a ceramic resonator may be connected across X1 and X2. If X2 is not used, it must be left unconnected. (O)
RESET
XRS 80 L10 M13 Device Reset (in) and Watchdog Reset (out).
Device reset. XRS causes the device to terminate execution. The PC will point to the address contained at the location 0x3FFFC0. When XRS is brought to a high level, execution begins at the location pointed to by the PC. This pin is driven low by the DSC when a watchdog reset occurs. During watchdog reset, the XRS pin is driven low for the watchdog reset duration of 512 OSCCLK cycles. (I/OD, ↑)
The output buffer of this pin is an open drain with an internal pullup. If this pin is driven by an external device, it should be done using an open-drain device.
ADC SIGNALS
ADCINA7 35 K4 K1 ADC Group A, Channel 7 input (I)
ADCINA6 36 J5 K2 ADC Group A, Channel 6 input (I)
ADCINA5 37 L1 L1 ADC Group A, Channel 5 input (I)
ADCINA4 38 L2 L2 ADC Group A, Channel 4 input (I)
ADCINA3 39 L3 L3 ADC Group A, Channel 3 input (I)
ADCINA2 40 M1 M1 ADC Group A, Channel 2 input (I)
ADCINA1 41 N1 M2 ADC Group A, Channel 1 input (I)
ADCINA0 42 M3 M3 ADC Group A, Channel 0 input (I)
ADCINB7 53 K5 N6 ADC Group B, Channel 7 input (I)
ADCINB6 52 P4 M6 ADC Group B, Channel 6 input (I)
ADCINB5 51 N4 N5 ADC Group B, Channel 5 input (I)
ADCINB4 50 M4 M5 ADC Group B, Channel 4 input (I)
ADCINB3 49 L4 N4 ADC Group B, Channel 3 input (I)
ADCINB2 48 P3 M4 ADC Group B, Channel 2 input (I)
ADCINB1 47 N3 N3 ADC Group B, Channel 1 input (I)
ADCINB0 46 P2 P3 ADC Group B, Channel 0 input (I)
ADCLO 43 M2 N2 Low Reference (connect to analog ground) (I)
ADCRESEXT 57 M5 P6 ADC External Current Bias Resistor. Connect a 22-kΩ resistor to analog ground.
ADCREFIN 54 L5 P7 External reference input (I)
ADCREFP 56 P5 P5 Internal Reference Positive Output. Requires a low ESR (under 1.5 Ω) ceramic bypass capacitor of 2.2 μF to analog ground. (O)
NOTE: Use the ADC Clock rate to derive the ESR specification from the capacitor data sheet that is used in the system.
ADCREFM 55 N5 P4 Internal Reference Medium Output. Requires a low ESR (under 1.5 Ω) ceramic bypass capacitor of 2.2 μF to analog ground. (O)
NOTE: Use the ADC Clock rate to derive the ESR specification from the capacitor data sheet that is used in the system.
CPU AND I/O POWER PINS
VDDA2 34 K2 K4 ADC Analog Power Pin
VSSA2 33 K3 P1 ADC Analog Ground Pin
VDDAIO 45 N2 L5 ADC Analog I/O Power Pin
VSSAIO 44 P1 N1 ADC Analog I/O Ground Pin
VDD1A18 31 J4 K3 ADC Analog Power Pin
VSS1AGND 32 K1 L4 ADC Analog Ground Pin
VDD2A18 59 M6 L6 ADC Analog Power Pin
VSS2AGND 58 K6 P2 ADC Analog Ground Pin
VDD 4 B1 D4 CPU and Logic Digital Power Pins
VDD 15 B5 D5
VDD 23 B11 D8
VDD 29 C8 D9
VDD 61 D13 E11
VDD 101 E9 F4
VDD 109 F3 F11
VDD 117 F13 H4
VDD 126 H1 J4
VDD 139 H12 J11
VDD 146 J2 K11
VDD 154 K14 L8
VDD 167 N6
VDDIO 9 A4 A13 Digital I/O Power Pin
VDDIO 71 B10 B1
VDDIO 93 E7 D7
VDDIO 107 E12 D11
VDDIO 121 F5 E4
VDDIO 143 L8 G4
VDDIO 159 H11 G11
VDDIO 170 N14 L10
VDDIO N14
VSS 3 A5 A1 Digital Ground Pins
VSS 8 A10 A2
VSS 14 A11 A14
VSS 22 B4 B14
VSS 30 C3 F6
VSS 60 C7 F7
VSS 70 C9 F8
VSS 83 D1 F9
VSS 92 D6 G6
VSS 103 D14 G7
VSS 106 E8 G8
VSS 108 E14 G9
VSS 118 F4 H6
VSS 120 F12 H7
VSS 125 G1 H8
VSS 140 H10 H9
VSS 144 H13 J6
VSS 147 J3 J7
VSS 155 J10 J8
VSS 160 J12 J9
VSS 166 M12 P13
VSS 171 N10 P14
VSS N11
VSS P6
VSS P8
GPIO AND PERIPHERAL SIGNALS
GPIO0
EPWM1A
-
-
5 C1 D1 General-purpose input/output 0 (I/O/Z)
Enhanced PWM1 Output A and HRPWM channel (O)
-
-
GPIO1
EPWM1B
ECAP6
MFSRB
6 D3 D2 General-purpose input/output 1 (I/O/Z)
Enhanced PWM1 Output B (O)
Enhanced Capture 6 input/output (I/O)
McBSP-B receive frame synch (I/O)
GPIO2
EPWM2A
-
-
7 D2 D3 General-purpose input/output 2 (I/O/Z)
Enhanced PWM2 Output A and HRPWM channel (O)
-
-
GPIO3
EPWM2B
ECAP5
MCLKRB
10 E4 E1 General-purpose input/output 3 (I/O/Z)
Enhanced PWM2 Output B (O)
Enhanced Capture 5 input/output (I/O)
McBSP-B receive clock (I/O)
GPIO4
EPWM3A
-
-
11 E2 E2 General-purpose input/output 4 (I/O/Z)
Enhanced PWM3 output A and HRPWM channel (O)
-
-
GPIO5
EPWM3B
MFSRA
ECAP1
12 E3 E3 General-purpose input/output 5 (I/O/Z)
Enhanced PWM3 output B (O)
McBSP-A receive frame synch (I/O)
Enhanced Capture input/output 1 (I/O)
GPIO6
EPWM4A
EPWMSYNCI
EPWMSYNCO
13 E1 F1 General-purpose input/output 6 (I/O/Z)
Enhanced PWM4 output A and HRPWM channel (O)
External ePWM sync pulse input (I)
External ePWM sync pulse output (O)
GPIO7
EPWM4B
MCLKRA
ECAP2
16 F2 F2 General-purpose input/output 7 (I/O/Z)
Enhanced PWM4 output B (O)
McBSP-A receive clock (I/O)
Enhanced capture input/output 2 (I/O)
GPIO8
EPWM5A
CANTXB
ADCSOCAO
17 F1 F3 General-purpose Input/Output 8 (I/O/Z)
Enhanced PWM5 output A and HRPWM channel (O)
Enhanced CAN-B transmit (O)
ADC start-of-conversion A (O)
GPIO9
EPWM5B
SCITXDB
ECAP3
18 G5 G1 General-purpose input/output 9 (I/O/Z)
Enhanced PWM5 output B (O)
SCI-B transmit data(O)
Enhanced capture input/output 3 (I/O)
GPIO10
EPWM6A
CANRXB
ADCSOCBO
19 G4 G2 General-purpose input/output 10 (I/O/Z)
Enhanced PWM6 output A and HRPWM channel (O)
Enhanced CAN-B receive (I)
ADC start-of-conversion B (O)
GPIO11
EPWM6B
SCIRXDB
ECAP4
20 G2 G3 General-purpose input/output 11 (I/O/Z)
Enhanced PWM6 output B (O)
SCI-B receive data (I)
Enhanced CAP Input/Output 4 (I/O)
GPIO12
TZ1
CANTXB
MDXB
21 G3 H1 General-purpose input/output 12 (I/O/Z)
Trip Zone input 1 (I)
Enhanced CAN-B transmit (O)
McBSP-B transmit serial data (O)
GPIO13
TZ2
CANRXB
MDRB
24 H3 H2 General-purpose input/output 13 (I/O/Z)
Trip Zone input 2 (I)
Enhanced CAN-B receive (I)
McBSP-B receive serial data (I)
GPIO14 25 H2 H3 General-purpose input/output 14 (I/O/Z)
TZ3/XHOLD Trip Zone input 3/External Hold Request. XHOLD, when active (low), requests the external interface (XINTF) to release the external bus and place all buses and strobes into a high-impedance state. To prevent this from happening when TZ3 signal goes active, disable this function by writing XINTCNF2[HOLD] = 1. If this is not done, the XINTF bus will go into high impedance anytime TZ3 goes low. On the ePWM side, TZn signals are ignored by default, unless they are enabled by the code. The XINTF will release the bus when any current access is complete and there are no pending accesses on the XINTF. (I)
SCITXDB SCI-B Transmit (O)
MCLKXB McBSP-B transmit clock (I/O)
GPIO15 26 H4 J1 General-purpose input/output 15 (I/O/Z)
TZ4/XHOLDA  Trip Zone input 4/External Hold Acknowledge. The pin function for this option is based on the direction chosen in the GPADIR register. If the pin is configured as an input, then TZ4 function is chosen. If the pin is configured as an output, then XHOLDA function is chosen. XHOLDA is driven active (low) when the XINTF has granted an XHOLD request. All XINTF buses and strobe signals will be in a high-impedance state. XHOLDA is released when the XHOLD signal is released. External devices should only drive the external bus when XHOLDA is active (low). (I/O)
SCIRXDB SCI-B receive (I)
MFSXB McBSP-B transmit frame synch (I/O)
GPIO16
SPISIMOA
CANTXB
TZ5
27 H5 J2 General-purpose input/output 16 (I/O/Z)
SPI slave in, master out (I/O)
Enhanced CAN-B transmit (O)
Trip Zone input 5 (I)
GPIO17
SPISOMIA
CANRXB
TZ6
28 J1 J3 General-purpose input/output 17 (I/O/Z)
SPI-A slave out, master in (I/O)
Enhanced CAN-B receive (I)
Trip zone input 6 (I)
GPIO18
SPICLKA
SCITXDB
CANRXA
62 L6 N8 General-purpose input/output 18 (I/O/Z)
SPI-A clock input/output (I/O)
SCI-B transmit (O)
Enhanced CAN-A receive (I)
GPIO19
SPISTEA
SCIRXDB
CANTXA
63 K7 M8 General-purpose input/output 19 (I/O/Z)
SPI-A slave transmit enable input/output (I/O)
SCI-B receive (I)
Enhanced CAN-A transmit (O)
GPIO20
EQEP1A
MDXA
CANTXB
64 L7 P9 General-purpose input/output 20 (I/O/Z)
Enhanced QEP1 input A (I)
McBSP-A transmit serial data (O)
Enhanced CAN-B transmit (O)
GPIO21
EQEP1B
MDRA
CANRXB
65 P7 N9 General-purpose input/output 21 (I/O/Z)
Enhanced QEP1 input B (I)
McBSP-A receive serial data (I)
Enhanced CAN-B receive (I)
GPIO22
EQEP1S
MCLKXA
SCITXDB
66 N7 M9 General-purpose input/output 22 (I/O/Z)
Enhanced QEP1 strobe (I/O)
McBSP-A transmit clock (I/O)
SCI-B transmit (O)
GPIO23
EQEP1I
MFSXA
SCIRXDB
67 M7 P10 General-purpose input/output 23 (I/O/Z)
Enhanced QEP1 index (I/O)
McBSP-A transmit frame synch (I/O)
SCI-B receive (I)
GPIO24
ECAP1
EQEP2A
MDXB
68 M8 N10 General-purpose input/output 24 (I/O/Z)
Enhanced capture 1 (I/O)
Enhanced QEP2 input A (I)
McBSP-B transmit serial data (O)
GPIO25
ECAP2
EQEP2B
MDRB
69 N8 M10 General-purpose input/output 25 (I/O/Z)
Enhanced capture 2 (I/O)
Enhanced QEP2 input B (I)
McBSP-B receive serial data (I)
GPIO26
ECAP3
EQEP2I
MCLKXB
72 K8 P11 General-purpose input/output 26 (I/O/Z)
Enhanced capture 3 (I/O)
Enhanced QEP2 index (I/O)
McBSP-B transmit clock (I/O)
GPIO27
ECAP4
EQEP2S
MFSXB
73 L9 N11 General-purpose input/output 27 (I/O/Z)
Enhanced capture 4 (I/O)
Enhanced QEP2 strobe (I/O)
McBSP-B transmit frame synch (I/O)
GPIO28
SCIRXDA
XZCS6
141 E10 D10 General-purpose input/output 28 (I/O/Z)
SCI receive data (I)
External Interface zone 6 chip select (O)
GPIO29
SCITXDA
XA19
2 C2 C1 General-purpose input/output 29. (I/O/Z)
SCI transmit data (O)
External Interface Address Line 19 (O)
GPIO30
CANRXA
XA18
1 B2 C2 General-purpose input/output 30 (I/O/Z)
Enhanced CAN-A receive (I)
External Interface Address Line 18 (O)
GPIO31
CANTXA
XA17
176 A2 B2 General-purpose input/output 31 (I/O/Z)
Enhanced CAN-A transmit (O)
External Interface Address Line 17 (O)
GPIO32
SDAA
EPWMSYNCI
ADCSOCAO
74 N9 M11 General-purpose input/output 32 (I/O/Z)
I2C data open-drain bidirectional port (I/OD)
Enhanced PWM external sync pulse input (I)
ADC start-of-conversion A (O)
GPIO33
SCLA
EPWMSYNCO
ADCSOCBO
75 P9 P12 General-purpose Input/Output 33 (I/O/Z)
I2C clock open-drain bidirectional port (I/OD)
Enhanced PWM external synch pulse output (O)
ADC start-of-conversion B (O)
GPIO34
ECAP1
XREADY
142 D10 A9 General-purpose Input/Output 34 (I/O/Z)
Enhanced Capture input/output 1 (I/O)
External Interface Ready signal. Note that this pin is always (directly) connected to the XINTF. If an application uses this pin as a GPIO while also using the XINTF, it should configure the XINTF to ignore READY.
GPIO35
SCITXDA
XR/W
148 A9 B9 General-purpose Input/Output 35 (I/O/Z)
SCI-A transmit data (O)
External Interface read, not write strobe
GPIO36
SCIRXDA
XZCS0
145 C10 C9 General-purpose Input/Output 36 (I/O/Z)
SCI receive data (I)
External Interface zone 0 chip select (O)
GPIO37
ECAP2
XZCS7
150 D9 B8 General-purpose Input/Output 37 (I/O/Z)
Enhanced Capture input/output 2 (I/O)
External Interface zone 7 chip select (O)
GPIO38
-
XWE0
137 D11 C10 General-purpose Input/Output 38 (I/O/Z)
-
External Interface Write Enable 0 (O)
GPIO39
-
XA16
175 B3 C3 General-purpose Input/Output 39 (I/O/Z)
-
External Interface Address Line 16 (O)
GPIO40
-
XA0/XWE1
151 D8 C8 General-purpose Input/Output 40 (I/O/Z)
-
External Interface Address Line 0/External Interface Write Enable 1 (O)
GPIO41
-
XA1
152 A8 A7 General-purpose Input/Output 41 (I/O/Z)
-
External Interface Address Line 1 (O)
GPIO42
-
XA2
153 B8 B7 General-purpose Input/Output 42 (I/O/Z)
-
External Interface Address Line 2 (O)
GPIO43
-
XA3
156 B7 C7 General-purpose Input/Output 43 (I/O/Z)
-
External Interface Address Line 3 (O)
GPIO44
-
XA4
157 A7 A6 General-purpose Input/Output 44 (I/O/Z)
-
External Interface Address Line 4 (O)
GPIO45
-
XA5
158 D7 B6 General-purpose Input/Output 45 (I/O/Z)
-
External Interface Address Line 5 (O)
GPIO46
-
XA6
161 B6 C6 General-purpose Input/Output 46 (I/O/Z)
-
External Interface Address Line 6 (O)
GPIO47
-
XA7
162 A6 D6 General-purpose Input/Output 47 (I/O/Z)
-
External Interface Address Line 7 (O)
GPIO48
ECAP5
XD31
88 P13 L14 General-purpose Input/Output 48 (I/O/Z)
Enhanced Capture input/output 5 (I/O)
External Interface Data Line 31 (I/O/Z)
GPIO49
ECAP6
XD30
89 N13 L13 General-purpose Input/Output 49 (I/O/Z)
Enhanced Capture input/output 6 (I/O)
External Interface Data Line 30 (I/O/Z)
GPIO50
EQEP1A
XD29
90 P14 L12 General-purpose Input/Output 50 (I/O/Z)
Enhanced QEP1 input A (I)
External Interface Data Line 29 (I/O/Z)
GPIO51
EQEP1B
XD28
91 M13 K14 General-purpose Input/Output 51 (I/O/Z)
Enhanced QEP1 input B (I)
External Interface Data Line 28 (I/O/Z)
GPIO52
EQEP1S
XD27
94 M14 K13 General-purpose Input/Output 52 (I/O/Z)
Enhanced QEP1 Strobe (I/O)
External Interface Data Line 27 (I/O/Z)
GPIO53
EQEP1I
XD26
95 L12 K12 General-purpose Input/Output 53 (I/O/Z)
Enhanced QEP1 lndex (I/O)
External Interface Data Line 26 (I/O/Z)
GPIO54
SPISIMOA
XD25
96 L13 J14 General-purpose Input/Output 54 (I/O/Z)
SPI-A slave in, master out (I/O)
External Interface Data Line 25 (I/O/Z)
GPIO55
SPISOMIA
XD24
97 L14 J13 General-purpose Input/Output 55 (I/O/Z)
SPI-A slave out, master in (I/O)
External Interface Data Line 24 (I/O/Z)
GPIO56
SPICLKA
XD23
98 K11 J12 General-purpose Input/Output 56 (I/O/Z)
SPI-A clock (I/O)
External Interface Data Line 23 (I/O/Z)
GPIO57
SPISTEA
XD22
99 K13 H13 General-purpose Input/Output 57 (I/O/Z)
SPI-A slave transmit enable (I/O)
External Interface Data Line 22 (I/O/Z)
GPIO58
MCLKRA
XD21
100 K12 H12 General-purpose Input/Output 58 (I/O/Z)
McBSP-A receive clock (I/O)
External Interface Data Line 21 (I/O/Z)
GPIO59
MFSRA
XD20
110 H14 H11 General-purpose Input/Output 59 (I/O/Z)
McBSP-A receive frame synch (I/O)
External Interface Data Line 20 (I/O/Z)
GPIO60
MCLKRB
XD19
111 G14 G12 General-purpose Input/Output 60 (I/O/Z)
McBSP-B receive clock (I/O)
External Interface Data Line 19 (I/O/Z)
GPIO61
MFSRB
XD18
112 G12 F14 General-purpose Input/Output 61 (I/O/Z)
McBSP-B receive frame synch (I/O)
External Interface Data Line 18 (I/O/Z)
GPIO62
SCIRXDC
XD17
113 G13 F13 General-purpose Input/Output 62 (I/O/Z)
SCI-C receive data (I)
External Interface Data Line 17 (I/O/Z)
GPIO63
SCITXDC
XD16
114 G11 F12 General-purpose Input/Output 63 (I/O/Z)
SCI-C transmit data (O)
External Interface Data Line 16 (I/O/Z)
GPIO64
-
XD15
115 G10 E14 General-purpose Input/Output 64 (I/O/Z)
-
External Interface Data Line 15 (I/O/Z)
GPIO65
-
XD14
116 F14 E13 General-purpose Input/Output 65 (I/O/Z)
-
External Interface Data Line 14 (I/O/Z)
GPIO66
-
XD13
119 F11 E12 General-purpose Input/Output 66 (I/O/Z)
-
External Interface Data Line 13 (I/O/Z)
GPIO67
-
XD12
122 E13 D14 General-purpose Input/Output 67 (I/O/Z)
-
External Interface Data Line 12 (I/O/Z)
GPIO68
-
XD11
123 E11 D13 General-purpose Input/Output 68 (I/O/Z)
-
External Interface Data Line 11 (I/O/Z)
GPIO69
-
XD10
124 F10 D12 General-purpose Input/Output 69 (I/O/Z)
-
External Interface Data Line 10 (I/O/Z)
GPIO70
-
XD9
127 D12 C14 General-purpose Input/Output 70 (I/O/Z)
-
External Interface Data Line 9 (I/O/Z)
GPIO71
-
XD8
128 C14 C13 General-purpose Input/Output 71 (I/O/Z)
-
External Interface Data Line 8 (I/O/Z)
GPIO72
-
XD7
129 B14 B13 General-purpose Input/Output 72 (I/O/Z)
-
External Interface Data Line 7 (I/O/Z)
GPIO73
-
XD6
130 C12 A12 General-purpose Input/Output 73 (I/O/Z)
-
External Interface Data Line 6 (I/O/Z)
GPIO74
-
XD5
131 C13 B12 General-purpose Input/Output 74 (I/O/Z)
-
External Interface Data Line 5 (I/O/Z)
GPIO75
-
XD4
132 A14 C12 General-purpose Input/Output 75 (I/O/Z)
-
External Interface Data Line 4 (I/O/Z)
GPIO76
-
XD3
133 B13 A11 General-purpose Input/Output 76 (I/O/Z)
-
External Interface Data Line 3 (I/O/Z)
GPIO77
-
XD2
134 A13 B11 General-purpose Input/Output 77 (I/O/Z)
-
External Interface Data Line 2 (I/O/Z)
GPIO78
-
XD1
135 B12 C11 General-purpose Input/Output 78 (I/O/Z)
-
External Interface Data Line 1 (I/O/Z)
GPIO79
-
XD0
136 A12 B10 General-purpose Input/Output 79 (I/O/Z)
-
External Interface Data Line 0 (I/O/Z)
GPIO80
-
XA8
163 C6 A5 General-purpose Input/Output 80 (I/O/Z)
-
External Interface Address Line 8 (O)
GPIO81
-
XA9
164 E6 B5 General-purpose Input/Output 81 (I/O/Z)
-
External Interface Address Line 9 (O)
GPIO82
-
XA10
165 C5 C5 General-purpose Input/Output 82 (I/O/Z)
-
External Interface Address Line 10 (O)
GPIO83
-
XA11
168 D5 A4 General-purpose Input/Output 83 (I/O/Z)
-
External Interface Address Line 11 (O)
GPIO84
-
XA12
169 E5 B4 General-purpose Input/Output 84 (I/O/Z)
 
External Interface Address Line 12 (O)
GPIO85
-
XA13
172 C4 C4 General-purpose Input/Output 85 (I/O/Z)
-
External Interface Address Line 13 (O)
GPIO86
-
XA14
173 D4 A3 General-purpose Input/Output 86 (I/O/Z)
-
External Interface Address Line 14 (O)
GPIO87
-
XA15
174 A3 B3 General-purpose Input/Output 87 (I/O/Z)
-
External Interface Address Line 15 (O)
XRD 149 B9 A8 External Interface Read Enable
I = Input, O = Output, Z = High impedance, OD = Open drain, ↑ = Pullup, ↓ = Pulldown