SPRS439O June 2007 – April 2019 TMS320F28232 , TMS320F28234 , TMS320F28235 , TMS320F28332 , TMS320F28333 , TMS320F28334 , TMS320F28335
PRODUCTION DATA.
Refer to the PDF data sheet for device specific package drawings
If the XREADY signal is sampled in the synchronous mode (USEREADY = 1, READYMODE = 0), then:
1 | Lead: | LR ≥ tc(XTIM) | ||
LW ≥ tc(XTIM) | ||||
2 | Active: | AR ≥ 2 × tc(XTIM) | ||
AW ≥ 2 × tc(XTIM) |
NOTE
Restriction does not include external hardware wait states.
These requirements result in the following XTIMING register configuration restrictions:
Examples of valid and invalid timing when using synchronous XREADY: