Refer to the PDF data sheet for device specific package drawings
If the HOLD mode bit is set while XHOLD and XHOLDA are both low (external bus accesses granted), the XHOLDA signal is forced high (at the end of the current cycle) and the external interface is taken out of high-impedance mode.
On a reset (XRS), the HOLD mode bit is set to 0. If the XHOLD signal is active low on a system reset, the bus and all signal strobes must be in high-impedance mode, and the XHOLDA signal is also driven active low.
When HOLD mode is enabled and XHOLDA is active low (external bus grant active), the CPU can still execute code from internal memory. If an access is made to the external interface, the CPU is stalled until the XHOLD signal is removed.
An external DMA request, when granted, places the following signals in a high-impedance mode:
|XWE0, XWE1, XRD||XZCS7|
All other signals not listed in this group remain in their default or functional operational modes during these signal events.