SPRS439O June   2007  – April 2019 TMS320F28232 , TMS320F28234 , TMS320F28235 , TMS320F28332 , TMS320F28333 , TMS320F28334 , TMS320F28335

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings – Automotive
    3. 5.3  ESD Ratings – Commercial
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Power Consumption Summary
      1. Table 5-1 TMS320F28335/F28235 Current Consumption by Power-Supply Pins at 150-MHz SYSCLKOUT
      2. Table 5-2 TMS320F28334/F28234 Current Consumption by Power-Supply Pins at 150-MHz SYSCLKOUT
      3. 5.5.1     Reducing Current Consumption
      4. 5.5.2     Current Consumption Graphs
    6. 5.6  Electrical Characteristics
    7. 5.7  Thermal Resistance Characteristics
      1. 5.7.1 PGF Package
      2. 5.7.2 PTP Package
      3. 5.7.3 ZHH Package
      4. 5.7.4 ZJZ Package
    8. 5.8  Thermal Design Considerations
    9. 5.9  Timing and Switching Characteristics
      1. 5.9.1 Timing Parameter Symbology
        1. 5.9.1.1 General Notes on Timing Parameters
        2. 5.9.1.2 Test Load Circuit
        3. 5.9.1.3 Device Clock Table
          1. Table 5-4 Clocking and Nomenclature (150-MHz Devices)
          2. Table 5-5 Clocking and Nomenclature (100-MHz Devices)
      2. 5.9.2 Power Sequencing
        1. 5.9.2.1   Power Management and Supervisory Circuit Solutions
        2. Table 5-6 Reset (XRS) Timing Requirements
      3. 5.9.3 Clock Requirements and Characteristics
        1. Table 5-7  Input Clock Frequency
        2. Table 5-8  XCLKIN Timing Requirements – PLL Enabled
        3. Table 5-9  XCLKIN Timing Requirements – PLL Disabled
        4. Table 5-10 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)
      4. 5.9.4 Peripherals
        1. 5.9.4.1 General-Purpose Input/Output (GPIO)
          1. 5.9.4.1.1 GPIO - Output Timing
            1. Table 5-11 General-Purpose Output Switching Characteristics
          2. 5.9.4.1.2 GPIO - Input Timing
            1. Table 5-12 General-Purpose Input Timing Requirements
          3. 5.9.4.1.3 Sampling Window Width for Input Signals
          4. 5.9.4.1.4 Low-Power Mode Wakeup Timing
            1. Table 5-13 IDLE Mode Timing Requirements
            2. Table 5-14 IDLE Mode Switching Characteristics
            3. Table 5-15 STANDBY Mode Timing Requirements
            4. Table 5-16 STANDBY Mode Switching Characteristics
            5. Table 5-17 HALT Mode Timing Requirements
            6. Table 5-18 HALT Mode Switching Characteristics
        2. 5.9.4.2 Enhanced Control Peripherals
          1. 5.9.4.2.1 Enhanced Pulse Width Modulator (ePWM) Timing
            1. Table 5-19 ePWM Timing Requirements
            2. Table 5-20 ePWM Switching Characteristics
          2. 5.9.4.2.2 Trip-Zone Input Timing
            1. Table 5-21 Trip-Zone Input Timing Requirements
          3. 5.9.4.2.3 High-Resolution PWM Timing
            1. Table 5-22 High-Resolution PWM Characteristics at SYSCLKOUT = (60–150 MHz)
          4. 5.9.4.2.4 Enhanced Capture (eCAP) Timing
            1. Table 5-23 Enhanced Capture (eCAP) Timing Requirements
            2. Table 5-24 eCAP Switching Characteristics
          5. 5.9.4.2.5 Enhanced Quadrature Encoder Pulse (eQEP) Timing
            1. Table 5-25 Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements
            2. Table 5-26 eQEP Switching Characteristics
          6. 5.9.4.2.6 ADC Start-of-Conversion Timing
            1. Table 5-27 External ADC Start-of-Conversion Switching Characteristics
        3. 5.9.4.3 External Interrupt Timing
          1. Table 5-28 External Interrupt Timing Requirements
          2. Table 5-29 External Interrupt Switching Characteristics
        4. 5.9.4.4 I2C Electrical Specification and Timing
          1. Table 5-30 I2C Timing
        5. 5.9.4.5 Serial Peripheral Interface (SPI) Timing
          1. 5.9.4.5.1 Master Mode Timing
            1. Table 5-31 SPI Master Mode External Timing (Clock Phase = 0)
            2. Table 5-32 SPI Master Mode External Timing (Clock Phase = 1)
          2. 5.9.4.5.2 Slave Mode Timing
            1. Table 5-33 SPI Slave Mode External Timing (Clock Phase = 0)
            2. Table 5-34 SPI Slave Mode External Timing (Clock Phase = 1)
        6. 5.9.4.6 Multichannel Buffered Serial Port (McBSP) Timing
          1. 5.9.4.6.1 McBSP Transmit and Receive Timing
            1. Table 5-35 McBSP Timing Requirements
            2. Table 5-36 McBSP Switching Characteristics
          2. 5.9.4.6.2 McBSP as SPI Master or Slave Timing
            1. Table 5-37 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)
            2. Table 5-38 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)
            3. Table 5-39 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)
            4. Table 5-40 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)
            5. Table 5-41 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)
            6. Table 5-42 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)
            7. Table 5-43 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1)
            8. Table 5-44 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1)
      5. 5.9.5 Emulator Connection Without Signal Buffering for the DSP
      6. 5.9.6 External Interface (XINTF) Timing
        1. 5.9.6.1 USEREADY = 0
        2. 5.9.6.2 Synchronous Mode (USEREADY = 1, READYMODE = 0)
        3. 5.9.6.3 Asynchronous Mode (USEREADY = 1, READYMODE = 1)
        4. 5.9.6.4 XINTF Signal Alignment to XCLKOUT
        5. 5.9.6.5 External Interface Read Timing
          1. Table 5-47 External Interface Read Timing Requirements
          2. Table 5-48 External Interface Read Switching Characteristics
        6. 5.9.6.6 External Interface Write Timing
          1. Table 5-49 External Interface Write Switching Characteristics
        7. 5.9.6.7 External Interface Ready-on-Read Timing With One External Wait State
          1. Table 5-50 External Interface Read Switching Characteristics (Ready-on-Read, One Wait State)
          2. Table 5-51 External Interface Read Timing Requirements (Ready-on-Read, One Wait State)
          3. Table 5-52 Synchronous XREADY Timing Requirements (Ready-on-Read, One Wait State)
          4. Table 5-53 Asynchronous XREADY Timing Requirements (Ready-on-Read, One Wait State)
        8. 5.9.6.8 External Interface Ready-on-Write Timing With One External Wait State
          1. Table 5-54 External Interface Write Switching Characteristics (Ready-on-Write, One Wait State)
          2. Table 5-55 Synchronous XREADY Timing Requirements (Ready-on-Write, One Wait State)
          3. Table 5-56 Asynchronous XREADY Timing Requirements (Ready-on-Write, One Wait State)
        9. 5.9.6.9 XHOLD and XHOLDA Timing
          1. Table 5-57 XHOLD/XHOLDA Timing Requirements (XCLKOUT = XTIMCLK)
          2. Table 5-58 XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK)
      7. 5.9.7 Flash Timing
        1. Table 5-59 Flash Endurance for A and S Temperature Material
        2. Table 5-60 Flash Endurance for Q Temperature Material
        3. Table 5-61 Flash Parameters at 150-MHz SYSCLKOUT
        4. Table 5-62 Flash/OTP Access Timing
        5. Table 5-63 Flash Data Retention Duration
    10. 5.10 On-Chip Analog-to-Digital Converter
      1. Table 5-65 ADC Electrical Characteristics (over recommended operating conditions)
      2. 5.10.1     ADC Power-Up Control Bit Timing
        1. Table 5-66 ADC Power-Up Delays
        2. Table 5-67 Typical Current Consumption for Different ADC Configurations (at 25-MHz ADCCLK)
      3. 5.10.2     Definitions
      4. 5.10.3     Sequential Sampling Mode (Single-Channel) (SMODE = 0)
        1. Table 5-68 Sequential Sampling Mode Timing
      5. 5.10.4     Simultaneous Sampling Mode (Dual-Channel) (SMODE = 1)
        1. Table 5-69 Simultaneous Sampling Mode Timing
      6. 5.10.5     Detailed Descriptions
    11. 5.11 Migrating Between F2833x Devices and F2823x Devices
  6. 6Detailed Description
    1. 6.1 Brief Descriptions
      1. 6.1.1  C28x CPU
      2. 6.1.2  Memory Bus (Harvard Bus Architecture)
      3. 6.1.3  Peripheral Bus
      4. 6.1.4  Real-Time JTAG and Analysis
      5. 6.1.5  External Interface (XINTF)
      6. 6.1.6  Flash
      7. 6.1.7  M0, M1 SARAMs
      8. 6.1.8  L0, L1, L2, L3, L4, L5, L6, L7 SARAMs
      9. 6.1.9  Boot ROM
        1. 6.1.9.1 Peripheral Pins Used by the Bootloader
      10. 6.1.10 Security
      11. 6.1.11 Peripheral Interrupt Expansion (PIE) Block
      12. 6.1.12 External Interrupts (XINT1–XINT7, XNMI)
      13. 6.1.13 Oscillator and PLL
      14. 6.1.14 Watchdog
      15. 6.1.15 Peripheral Clocking
      16. 6.1.16 Low-Power Modes
      17. 6.1.17 Peripheral Frames 0, 1, 2, 3 (PFn)
      18. 6.1.18 General-Purpose Input/Output (GPIO) Multiplexer
      19. 6.1.19 32-Bit CPU-Timers (0, 1, 2)
      20. 6.1.20 Control Peripherals
      21. 6.1.21 Serial Port Peripherals
    2. 6.2 Peripherals
      1. 6.2.1  DMA Overview
      2. 6.2.2  32-Bit CPU-Timer 0, CPU-Timer 1, CPU-Timer 2
      3. 6.2.3  Enhanced PWM Modules
      4. 6.2.4  High-Resolution PWM (HRPWM)
      5. 6.2.5  Enhanced CAP Modules
      6. 6.2.6  Enhanced QEP Modules
      7. 6.2.7  Analog-to-Digital Converter (ADC) Module
        1. 6.2.7.1 ADC Connections if the ADC Is Not Used
        2. 6.2.7.2 ADC Registers
        3. 6.2.7.3 ADC Calibration
      8. 6.2.8  Multichannel Buffered Serial Port (McBSP) Module
      9. 6.2.9  Enhanced Controller Area Network (eCAN) Modules (eCAN-A and eCAN-B)
      10. 6.2.10 Serial Communications Interface (SCI) Modules (SCI-A, SCI-B, SCI-C)
      11. 6.2.11 Serial Peripheral Interface (SPI) Module (SPI-A)
      12. 6.2.12 Inter-Integrated Circuit (I2C)
      13. 6.2.13 GPIO MUX
      14. 6.2.14 External Interface (XINTF)
    3. 6.3 Memory Maps
    4. 6.4 Register Map
      1. 6.4.1 Device Emulation Registers
    5. 6.5 Interrupts
      1. 6.5.1 External Interrupts
    6. 6.6 System Control
      1. 6.6.1 OSC and PLL Block
        1. 6.6.1.1 External Reference Oscillator Clock Option
        2. 6.6.1.2 PLL-Based Clock Module
        3. 6.6.1.3 Loss of Input Clock
      2. 6.6.2 Watchdog Block
    7. 6.7 Low-Power Modes Block
  7. 7Applications, Implementation, and Layout
    1. 7.1 TI Design or Reference Design
  8. 8Device and Documentation Support
    1. 8.1 Getting Started
    2. 8.2 Device and Development Support Tool Nomenclature
    3. 8.3 Tools and Software
    4. 8.4 Documentation Support
    5. 8.5 Related Links
    6. 8.6 Community Resources
    7. 8.7 Trademarks
    8. 8.8 Electrostatic Discharge Caution
    9. 8.9 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ZHH|179
  • ZJZ|176
  • ZAY|179
  • PGF|176
  • PTP|176
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Enhanced Controller Area Network (eCAN) Modules (eCAN-A and eCAN-B)

The CAN module has the following features:

  • Fully compliant with ISO 11898-1 (CAN 2.0B)
  • Supports data rates up to 1 Mbps
  • Thirty-two mailboxes, each with the following properties:
    • Configurable as receive or transmit
    • Configurable with standard or extended identifier
    • Has a programmable receive mask
    • Supports data and remote frame
    • Composed of 0 to 8 bytes of data
    • Uses a 32-bit timestamp on receive and transmit message
    • Protects against reception of new message
    • Holds the dynamically programmable priority of transmit message
    • Employs a programmable interrupt scheme with two interrupt levels
    • Employs a programmable alarm on transmission or reception time-out
  • Low-power mode
  • Programmable wake-up on bus activity
  • Automatic reply to a remote request message
  • Automatic retransmission of a frame in case of loss of arbitration or error
  • 32-bit local network time counter synchronized by a specific message (communication in conjunction with mailbox 16)
  • Self-test mode
    • Operates in a loopback mode receiving its own message. A "dummy" acknowledge is provided, thereby eliminating the need for another node to provide the acknowledge bit.

NOTE

For a SYSCLKOUT of 100 MHz, the smallest bit rate possible is 7.812 kbps.

For a SYSCLKOUT of 150 MHz, the smallest bit rate possible is 11.719 kbps.

The F2833x/F2823x CAN has passed the conformance test per ISO/DIS 16845. Contact TI for test report and exceptions.

TMS320F28335 TMS320F28334 TMS320F28333 TMS320F28332 TMS320F28235 TMS320F28234 TMS320F28232 fbd_ecan_prs439.gifFigure 6-12 eCAN Block Diagram and Interface Circuit

Table 6-10 3.3-V eCAN Transceivers

PART NUMBER SUPPLY VOLTAGE LOW-POWER
MODE
SLOPE
CONTROL
VREF OTHER TA
SN65HVD230 3.3 V Standby Adjustable Yes –40°C to 85°C
SN65HVD230Q 3.3 V Standby Adjustable Yes –40°C to 125°C
SN65HVD231 3.3 V Sleep Adjustable Yes –40°C to 85°C
SN65HVD231Q 3.3 V Sleep Adjustable Yes –40°C to 125°C
SN65HVD232 3.3 V None None None –40°C to 85°C
SN65HVD232Q 3.3 V None None None –40°C to 125°C
SN65HVD233 3.3 V Standby Adjustable None Diagnostic Loopback –40°C to 125°C
SN65HVD234 3.3 V Standby and Sleep Adjustable None –40°C to 125°C
SN65HVD235 3.3 V Standby Adjustable None Autobaud Loopback –40°C to 125°C
TMS320F28335 TMS320F28334 TMS320F28333 TMS320F28332 TMS320F28235 TMS320F28234 TMS320F28232 mm_ecana_prs439.gifFigure 6-13 eCAN-A Memory Map

NOTE

If the eCAN module is not used in an application, the RAM available (LAM, MOTS, MOTO, and mailbox RAM) can be used as general-purpose RAM. The CAN module clock should be enabled for this.

TMS320F28335 TMS320F28334 TMS320F28333 TMS320F28332 TMS320F28235 TMS320F28234 TMS320F28232 mm_ecanb_prs439.gifFigure 6-14 eCAN-B Memory Map

The CAN registers listed in Table 6-11 are used by the CPU to configure and control the CAN controller and the message objects. eCAN control registers only support 32-bit read/write operations. Mailbox RAM can be accessed as 16 bits or 32 bits. Thirty-two-bit accesses are aligned to an even boundary.

Table 6-11 CAN Register Map(1)

REGISTER NAME eCAN-A
ADDRESS
eCAN-B
ADDRESS
SIZE
(x32)
DESCRIPTION
CANME 0x6000 0x6200 1 Mailbox enable
CANMD 0x6002 0x6202 1 Mailbox direction
CANTRS 0x6004 0x6204 1 Transmit request set
CANTRR 0x6006 0x6206 1 Transmit request reset
CANTA 0x6008 0x6208 1 Transmission acknowledge
CANAA 0x600A 0x620A 1 Abort acknowledge
CANRMP 0x600C 0x620C 1 Receive message pending
CANRML 0x600E 0x620E 1 Receive message lost
CANRFP 0x6010 0x6210 1 Remote frame pending
CANGAM 0x6012 0x6212 1 Global acceptance mask
CANMC 0x6014 0x6214 1 Master control
CANBTC 0x6016 0x6216 1 Bit-timing configuration
CANES 0x6018 0x6218 1 Error and status
CANTEC 0x601A 0x621A 1 Transmit error counter
CANREC 0x601C 0x621C 1 Receive error counter
CANGIF0 0x601E 0x621E 1 Global interrupt flag 0
CANGIM 0x6020 0x6220 1 Global interrupt mask
CANGIF1 0x6022 0x6222 1 Global interrupt flag 1
CANMIM 0x6024 0x6224 1 Mailbox interrupt mask
CANMIL 0x6026 0x6226 1 Mailbox interrupt level
CANOPC 0x6028 0x6228 1 Overwrite protection control
CANTIOC 0x602A 0x622A 1 TX I/O control
CANRIOC 0x602C 0x622C 1 RX I/O control
CANTSC 0x602E 0x622E 1 Timestamp counter (Reserved in SCC mode)
CANTOC 0x6030 0x6230 1 Time-out control (Reserved in SCC mode)
CANTOS 0x6032 0x6232 1 Time-out status (Reserved in SCC mode)
These registers are mapped to Peripheral Frame 1.