If the XREADY signal is sampled in the synchronous mode (USEREADY = 1, READYMODE = 0), then:
|1||Lead:||LR ≥ tc(XTIM)|
|LW ≥ tc(XTIM)|
|2||Active:||AR ≥ 2 × tc(XTIM)|
|AW ≥ 2 × tc(XTIM)|
Restriction does not include external hardware wait states.
These requirements result in the following XTIMING register configuration restrictions:
Examples of valid and invalid timing when using synchronous XREADY: