Refer to the PDF data sheet for device specific package drawings
Table 5-51 lists the ADC timings in 12-bit mode (SYSCLK cycles). Table 5-52 lists the ADC timings in 16-bit mode. Figure 5-35 and Figure 5-36 show the ADC conversion timings for two SOCs given the following assumptions:
|tSH||The duration of the S+H window.
At the end of this window, the value on the S+H capacitor becomes the voltage to be converted into a digital value. The duration is given by (ACQPS + 1) SYSCLK cycles. ACQPS can be configured individually for each SOC, so tSH will not necessarily be the same for different SOCs.
Note: The value on the S+H capacitor will be captured approximately 5 ns before the end of the S+H window regardless of device clock settings.
|tLAT||The time from the end of the S+H window until the ADC conversion results latch in the ADCRESULTx register.
If the ADCRESULTx register is read before this time, the previous conversion results will be returned.
|tEOC||The time from the end of the S+H window until the next ADC conversion S+H window can begin. The subsequent sample can start before the conversion results are latched.|
|tINT||The time from the end of the S+H window until an ADCINT flag is set (if configured).
If the INTPULSEPOS bit in the ADCCTL1 register is set, tINT will coincide with the conversion results being latched into the result register.
If the INTPULSEPOS bit is 0, tINT will coincide with the end of the S+H window. If tINT triggers a read of the ADC result register (directly through DMA or indirectly by triggering an ISR that reads the result), care must be taken to ensure the read occurs after the results latch (otherwise, the previous results will be read).