SPRS880L December   2013  – March 2020 TMS320F28374D , TMS320F28375D , TMS320F28376D , TMS320F28377D , TMS320F28378D , TMS320F28379D

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
      1. Table 4-1 Signal Descriptions
    3. 4.3 Pins With Internal Pullup and Pulldown
    4. 4.4 Pin Multiplexing
      1. 4.4.1 GPIO Muxed Pins
      2. 4.4.2 Input X-BAR
      3. 4.4.3 Output X-BAR and ePWM X-BAR
      4. 4.4.4 USB Pin Muxing
      5. 4.4.5 High-Speed SPI Pin Muxing
    5. 4.5 Connections for Unused Pins
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings – Commercial
    3. 5.3  ESD Ratings – Automotive
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Power Consumption Summary
      1. Table 5-1 Device Current Consumption at 200-MHz SYSCLK
      2. 5.5.1     Current Consumption Graphs
      3. 5.5.2     Reducing Current Consumption
    6. 5.6  Electrical Characteristics
    7. 5.7  Thermal Resistance Characteristics
      1. 5.7.1 ZWT Package
      2. 5.7.2 PTP Package
      3. 5.7.3 PZP Package
    8. 5.8  Thermal Design Considerations
    9. 5.9  System
      1. 5.9.1 Power Sequencing
        1. 5.9.1.1 Signal Pin Requirements
        2. 5.9.1.2 VDDIO, VDDA, VDD3VFL, and VDDOSC Requirements
        3. 5.9.1.3 VDD Requirements
        4. 5.9.1.4 Supply Ramp Rate
          1. Table 5-3 Supply Ramp Rate
        5. 5.9.1.5 Supply Supervision
      2. 5.9.2 Reset Timing
        1. 5.9.2.1 Reset Sources
        2. 5.9.2.2 Reset Electrical Data and Timing
          1. Table 5-4 Reset (XRS) Timing Requirements
          2. Table 5-5 Reset (XRS) Switching Characteristics
      3. 5.9.3 Clock Specifications
        1. 5.9.3.1 Clock Sources
        2. 5.9.3.2 Clock Frequencies, Requirements, and Characteristics
          1. 5.9.3.2.1 Input Clock Frequency and Timing Requirements, PLL Lock Times
            1. Table 5-7  Input Clock Frequency
            2. Table 5-8  X1 Input Level Characteristics When Using an External Clock Source (Not a Crystal)
            3. Table 5-9  X1 Timing Requirements
            4. Table 5-10 AUXCLKIN Timing Requirements
            5. Table 5-11 PLL Lock Times
          2. 5.9.3.2.2 Internal Clock Frequencies
            1. Table 5-12 Internal Clock Frequencies
          3. 5.9.3.2.3 Output Clock Frequency and Switching Characteristics
            1. Table 5-13 Output Clock Frequency
            2. Table 5-14 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)
        3. 5.9.3.3 Input Clocks and PLLs
        4. 5.9.3.4 Crystal Oscillator
          1. Table 5-15 Crystal Oscillator Parameters
          2. Table 5-17 Crystal Oscillator Electrical Characteristics
        5. 5.9.3.5 Internal Oscillators
          1. Table 5-18 Internal Oscillator Electrical Characteristics
      4. 5.9.4 Flash Parameters
        1. Table 5-20 Flash Parameters
      5. 5.9.5 Emulation/JTAG
        1. 5.9.5.1 JTAG Electrical Data and Timing
          1. Table 5-21 JTAG Timing Requirements
          2. Table 5-22 JTAG Switching Characteristics
      6. 5.9.6 GPIO Electrical Data and Timing
        1. 5.9.6.1 GPIO - Output Timing
          1. Table 5-23 General-Purpose Output Switching Characteristics
        2. 5.9.6.2 GPIO - Input Timing
          1. Table 5-24 General-Purpose Input Timing Requirements
        3. 5.9.6.3 Sampling Window Width for Input Signals
      7. 5.9.7 Interrupts
        1. 5.9.7.1 External Interrupt (XINT) Electrical Data and Timing
          1. Table 5-25 External Interrupt Timing Requirements
          2. Table 5-26 External Interrupt Switching Characteristics
      8. 5.9.8 Low-Power Modes
        1. 5.9.8.1 Clock-Gating Low-Power Modes
        2. 5.9.8.2 Power-Gating Low-Power Modes
        3. 5.9.8.3 Low-Power Mode Wakeup Timing
          1. Table 5-29 IDLE Mode Timing Requirements
          2. Table 5-30 IDLE Mode Switching Characteristics
          3. Table 5-31 STANDBY Mode Timing Requirements
          4. Table 5-32 STANDBY Mode Switching Characteristics
          5. Table 5-33 HALT Mode Timing Requirements
          6. Table 5-34 HALT Mode Switching Characteristics
          7. Table 5-35 HIBERNATE Mode Timing Requirements
          8. Table 5-36 HIBERNATE Mode Switching Characteristics
      9. 5.9.9 External Memory Interface (EMIF)
        1. 5.9.9.1 Asynchronous Memory Support
        2. 5.9.9.2 Synchronous DRAM Support
        3. 5.9.9.3 EMIF Electrical Data and Timing
          1. 5.9.9.3.1 Asynchronous RAM
            1. Table 5-37 EMIF Asynchronous Memory Timing Requirements
            2. Table 5-38 EMIF Asynchronous Memory Switching Characteristics
          2. 5.9.9.3.2 Synchronous RAM
            1. Table 5-39 EMIF Synchronous Memory Timing Requirements
            2. Table 5-40 EMIF Synchronous Memory Switching Characteristics
    10. 5.10 Analog Peripherals
      1. 5.10.1 Analog-to-Digital Converter (ADC)
        1. 5.10.1.1 ADC Configurability
          1. 5.10.1.1.1 Signal Mode
        2. 5.10.1.2 ADC Electrical Data and Timing
          1. Table 5-42 ADC Operating Conditions (16-Bit Differential Mode)
          2. Table 5-43 ADC Characteristics (16-Bit Differential Mode)
          3. Table 5-44 ADC Operating Conditions (12-Bit Single-Ended Mode)
          4. Table 5-45 ADC Characteristics (12-Bit Single-Ended Mode)
          5. Table 5-46 ADCEXTSOC Timing Requirements
          6. 5.10.1.2.1 ADC Input Models
            1. Table 5-47 Differential Input Model Parameters
            2. Table 5-48 Single-Ended Input Model Parameters
          7. 5.10.1.2.2 ADC Timing Diagrams
            1. Table 5-51 ADC Timings in 12-Bit Mode (SYSCLK Cycles)
            2. Table 5-52 ADC Timings in 16-Bit Mode
        3. 5.10.1.3 Temperature Sensor Electrical Data and Timing
          1. Table 5-53 Temperature Sensor Electrical Characteristics
      2. 5.10.2 Comparator Subsystem (CMPSS)
        1. 5.10.2.1 CMPSS Electrical Data and Timing
          1. Table 5-54 Comparator Electrical Characteristics
          2. Table 5-55 CMPSS DAC Static Electrical Characteristics
      3. 5.10.3 Buffered Digital-to-Analog Converter (DAC)
        1. 5.10.3.1 Buffered DAC Electrical Data and Timing
          1. Table 5-56 Buffered DAC Electrical Characteristics
    11. 5.11 Control Peripherals
      1. 5.11.1 Enhanced Capture (eCAP)
        1. 5.11.1.1 eCAP Electrical Data and Timing
          1. Table 5-57 eCAP Timing Requirement
          2. Table 5-58 eCAP Switching Characteristics
      2. 5.11.2 Enhanced Pulse Width Modulator (ePWM)
        1. 5.11.2.1 Control Peripherals Synchronization
        2. 5.11.2.2 ePWM Electrical Data and Timing
          1. Table 5-59 ePWM Timing Requirements
          2. Table 5-60 ePWM Switching Characteristics
          3. 5.11.2.2.1 Trip-Zone Input Timing
            1. Table 5-61 Trip-Zone Input Timing Requirements
        3. 5.11.2.3 External ADC Start-of-Conversion Electrical Data and Timing
          1. Table 5-62 External ADC Start-of-Conversion Switching Characteristics
      3. 5.11.3 Enhanced Quadrature Encoder Pulse (eQEP)
        1. 5.11.3.1 eQEP Electrical Data and Timing
          1. Table 5-63 eQEP Timing Requirements
          2. Table 5-64 eQEP Switching Characteristics
      4. 5.11.4 High-Resolution Pulse Width Modulator (HRPWM)
        1. 5.11.4.1 HRPWM Electrical Data and Timing
          1. Table 5-65 High-Resolution PWM Timing Requirements
          2. Table 5-66 High-Resolution PWM Characteristics
      5. 5.11.5 Sigma-Delta Filter Module (SDFM)
        1. 5.11.5.1 SDFM Electrical Data and Timing (Using ASYNC)
          1. Table 5-67 SDFM Timing Requirements When Using Asynchronous GPIO (ASYNC) Option
        2. 5.11.5.2 SDFM Electrical Data and Timing (Using 3-Sample GPIO Input Qualification)
          1. Table 5-68 SDFM Timing Requirements When Using GPIO Input Qualification (3-Sample Window) Option
    12. 5.12 Communications Peripherals
      1. 5.12.1 Controller Area Network (CAN)
      2. 5.12.2 Inter-Integrated Circuit (I2C)
        1. 5.12.2.1 I2C Electrical Data and Timing
          1. Table 5-69 I2C Timing Requirements
          2. Table 5-70 I2C Switching Characteristics
      3. 5.12.3 Multichannel Buffered Serial Port (McBSP)
        1. 5.12.3.1 McBSP Electrical Data and Timing
          1. 5.12.3.1.1 McBSP Transmit and Receive Timing
            1. Table 5-71 McBSP Timing Requirements
            2. Table 5-72 McBSP Switching Characteristics
          2. 5.12.3.1.2 McBSP as SPI Master or Slave Timing
            1. Table 5-73 McBSP as SPI Master Timing Requirements
            2. Table 5-74 McBSP as SPI Master Switching Characteristics
            3. Table 5-75 McBSP as SPI Slave Timing Requirements
            4. Table 5-76 McBSP as SPI Slave Switching Characteristics
      4. 5.12.4 Serial Communications Interface (SCI)
      5. 5.12.5 Serial Peripheral Interface (SPI)
        1. 5.12.5.1 SPI Electrical Data and Timing
          1. 5.12.5.1.1 SPI Master Mode Timings
            1. Table 5-77 SPI Master Mode Timing Requirements
            2. Table 5-78 SPI Master Mode Switching Characteristics (Clock Phase = 0)
            3. Table 5-79 SPI Master Mode Switching Characteristics (Clock Phase = 1)
          2. 5.12.5.1.2 SPI Slave Mode Timings
            1. Table 5-80 SPI Slave Mode Timing Requirements
            2. Table 5-81 SPI Slave Mode Switching Characteristics
      6. 5.12.6 Universal Serial Bus (USB) Controller
        1. 5.12.6.1 USB Electrical Data and Timing
          1. Table 5-82 USB Input Ports DP and DM Timing Requirements
          2. Table 5-83 USB Output Ports DP and DM Switching Characteristics
      7. 5.12.7 Universal Parallel Port (uPP) Interface
        1. 5.12.7.1 uPP Electrical Data and Timing
          1. Table 5-84 uPP Timing Requirements
          2. Table 5-85 uPP Switching Characteristics
  6. 6Detailed Description
    1. 6.1  Overview
    2. 6.2  Functional Block Diagram
    3. 6.3  Memory
      1. 6.3.1 C28x Memory Map
      2. 6.3.2 Flash Memory Map
      3. 6.3.3 EMIF Chip Select Memory Map
      4. 6.3.4 Peripheral Registers Memory Map
      5. 6.3.5 Memory Types
        1. 6.3.5.1 Dedicated RAM (Mx and Dx RAM)
        2. 6.3.5.2 Local Shared RAM (LSx RAM)
        3. 6.3.5.3 Global Shared RAM (GSx RAM)
        4. 6.3.5.4 CPU Message RAM (CPU MSGRAM)
        5. 6.3.5.5 CLA Message RAM (CLA MSGRAM)
    4. 6.4  Identification
    5. 6.5  Bus Architecture – Peripheral Connectivity
    6. 6.6  C28x Processor
      1. 6.6.1 Floating-Point Unit
      2. 6.6.2 Trigonometric Math Unit
      3. 6.6.3 Viterbi, Complex Math, and CRC Unit II (VCU-II)
    7. 6.7  Control Law Accelerator
    8. 6.8  Direct Memory Access
    9. 6.9  Interprocessor Communication Module
    10. 6.10 Boot ROM and Peripheral Booting
      1. 6.10.1 EMU Boot or Emulation Boot
      2. 6.10.2 WAIT Boot Mode
      3. 6.10.3 Get Mode
      4. 6.10.4 Peripheral Pins Used by Bootloaders
    11. 6.11 Dual Code Security Module
    12. 6.12 Timers
    13. 6.13 Nonmaskable Interrupt With Watchdog Timer (NMIWD)
    14. 6.14 Watchdog
    15. 6.15 Configurable Logic Block (CLB)
    16. 6.16 Functional Safety
  7. 7Applications, Implementation, and Layout
    1. 7.1 TI Reference Design
  8. 8Device and Documentation Support
    1. 8.1 Device and Development Support Tool Nomenclature
    2. 8.2 Markings
    3. 8.3 Tools and Software
    4. 8.4 Documentation Support
    5. 8.5 Related Links
    6. 8.6 Support Resources
    7. 8.7 Trademarks
    8. 8.8 Electrostatic Discharge Caution
    9. 8.9 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ZWT|337
  • PTP|176
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Device Comparison

Table 3-1 lists the features of each 2837xD device.

Table 3-1 Device Comparison

FEATURE(1) 28379D 28378D 28377D 28376D 28375D 28374D
Package Type
(ZWT is an nFBGA package.
PTP is an HLQFP package.
PZP is an HTQFP package.)
337-Ball
ZWT
176-Pin
PTP
176-Pin
PTP
337-Ball
ZWT
176-Pin
PTP
337-Ball
ZWT
176-Pin
PTP
337-Ball
ZWT
176-Pin
PTP
100-Pin
PZP
337-Ball
ZWT
176-Pin
PTP
Processor and Accelerators
C28x Number 2
Frequency (MHz) 200
Floating-Point Unit (FPU) Yes
VCU-II Yes
TMU – Type 0 Yes
CLA – Type 1 Number 2
Frequency (MHz) 200
6-Channel DMA – Type 0 2
Memory
Flash (16-bit words) 1MB (512KW)
[512KB (256KW) per CPU]
1MB (512KW)
[512KB (256KW) per CPU]
1MB (512KW)
[512KB (256KW) per CPU]
512KB (256KW)
[256KB (128KW) per CPU]
1MB (512KW)
[512KB (256KW) per CPU]
512KB (256KW)
[256KB (128KW) per CPU]
RAM (16-bit words) Dedicated and Local Shared RAM 72KB (36KW)
[36KB (18KW) per CPU]
Global Shared RAM 128KB (64KW) 128KB (64KW) 128KB (64KW) 96KB (48KW) 128KB (64KW) 96KB (48KW)
Message RAM 4KB (2KW)
[2KB (1KW) per CPU]
Total RAM 204KB (102KW) 204KB (102KW) 204KB (102KW) 172KB (86KW) 204KB (102KW) 172KB (86KW)
Code security for on-chip flash, RAM, and OTP blocks Yes
Boot ROM Yes
System
Configurable Logic Block (CLB) 4 tiles No
32-bit CPU timers 6 (3 per CPU)
Watchdog timers 2 (1 per CPU)
Nonmaskable Interrupt Watchdog (NMIWD) timers 2 (1 per CPU)
Crystal oscillator/External clock input 1
0-pin internal oscillator 2
I/O pins (shared) GPIO 169 97 97 169 97 169 97 169 97 41 169 97
External interrupts 5
EMIF EMIF1 (16-bit or 32-bit) 1 1 1
EMIF2 (16-bit) 1 1 1 1 1
Analog Peripherals
ADC 16-bit mode MSPS 1.1 1.1
Conversion Time (ns)(2) 915 915
Input pins 24 20 24 20 24 20
Channels (differential) 12 9 12 9 12 9
ADC 12-bit mode MSPS 3.5
Conversion Time (ns)(2) 280
Input pins 24 20 20 24 20 24 20 24 20 14 24 20
Channels (single-ended) 24 20 20 24 20 24 20 24 20 14 24 20
Number of 16-bit or 12-bit ADCs 4 4
Number of 12-bit only ADCs 4 4 2 4
Temperature sensor 1
CMPSS (each CMPSS has two comparators and two internal DACs) 8 8 4 8
Buffered DAC 3
Control Peripherals(3)
eCAP inputs – Type 0 6
Enhanced Pulse Width Modulator (ePWM) channels – Type 4 24 24 15 24
eQEP modules – Type 0 3 3 2 3
High-resolution ePWM channels – Type 4 16 16 9 16
SDFM channels – Type 0 8 8 6 8
Communication Peripherals(3)
Controller Area Network (CAN) – Type 0(4) 2
Inter-Integrated Circuit (I2C) – Type 0 2
Multichannel Buffered Serial Port (McBSP) – Type 1 2
SCI – Type 0 4 4 3 4
Serial Peripheral Interface (SPI) – Type 2 3
USB – Type 0 1
uPP – Type 0 1
Temperature and Qualification
Junction Temperature (TJ) T: –40°C to 105°C Yes No Yes Yes No Yes
S: –40°C to 125°C Yes
Q: –40°C to 150°C(5) No Yes No Yes No
Free-Air Temperature (TA) Q: –40°C to 125°C(5) No Yes No Yes No
A type change represents a major functional feature difference in a peripheral module. Within a peripheral type, there may be minor differences between devices that do not affect the basic functionality of the module. For more information, see the C2000 Real-Time Control Peripherals Reference Guide.
Time between start of sample-and-hold window to start of sample-and-hold window of the next conversion.
For devices that are available in more than one package, the peripheral count listed in the smaller package is reduced because the smaller package has less device pins available. The number of peripherals internally present on the device is not reduced compared to the largest package offered within a part number. See Section 4 to identify which peripheral instances are accessible on pins in the smaller package.
The CAN module uses the IP known as D_CAN. This document uses the names CAN and D_CAN interchangeably to reference this peripheral.
The letter Q refers to AEC Q100 qualification for automotive applications.