Refer to the PDF data sheet for device specific package drawings
The on-chip flash memory is tightly integrated to the CPU, allowing code execution directly from flash through 128-bit-wide prefetch reads and a pipeline buffer. Flash performance for sequential code is equal to execution from RAM. Factoring in discontinuities, most applications will run with an efficiency of approximately 80% relative to code executing from RAM. This flash efficiency lets designers realize a 2× improvement in performance when migrating from the previous generation of MCUs.
This device also has an OTP (One-Time-Programmable) sector used for the dual code security module (DCSM), which cannot be erased after it is programmed.
|CPUCLK (MHz)||MINIMUM WAIT STATES (1)|
|EXTERNAL OSCILLATOR OR CRYSTAL||INTOSC1 OR INTOSC2|
|150 < CPUCLK ≤ 200||145 < CPUCLK ≤ 194||3|
|100 < CPUCLK ≤ 150||97 < CPUCLK ≤ 145||2|
|50 < CPUCLK ≤ 100||48 < CPUCLK ≤ 97||1|
|CPUCLK ≤ 50||CPUCLK ≤ 48||0|