Refer to the PDF data sheet for device specific package drawings
Table 5-7 shows the frequency requirements for the input clocks. Table 5-16 shows the crystal equivalent series resistance requirements. Table 5-8 shows the X1 input level characteristics when using an external clock source. Table 5-9 and Table 5-10 show the timing requirements for the input clocks. Table 5-11 shows the PLL lock times for the Main PLL and the USB PLL.