5.12.3 Multichannel Buffered Serial Port (McBSP)
The McBSP module has the following features:
- Compatible with McBSP in TMS320C28x and TMS320F28x DSP devices
- Full-duplex communication
- Double-buffered data registers that allow a continuous data stream
- Independent framing and clocking for receive and transmit
- External shift clock generation or an internal programmable frequency shift clock
- 8-bit data transfer mode can be configured to transmit with LSB or MSB first
- Programmable polarity for both frame synchronization and data clocks
- Highly programmable internal clock and frame generation
- Direct interface to industry-standard CODECs, Analog Interface Chips (AICs), and other serially connected A/D and D/A devices
- Supports AC97, I2S, and SPI protocols
- McBSP clock rate,
where CLKSRG source could be LSPCLK, CLKX, or CLKR.
Figure 5-63 shows the block diagram of the McBSP module.
Figure 5-63 McBSP Block Diagram