Refer to the PDF data sheet for device specific package drawings
The internal VREG is not supported. The VREGENZ pin must be tied to VDDIO and an external source used to supply 1.2 V to VDD. During the ramp, VDD should be kept no more than 0.3 V above VDDIO.
VDDOSC and VDD must be powered on and off at the same time. VDDOSC should not be powered on when VDD is off. For applications not powering VDDOSC and VDD at the same time, see the "INTOSC: VDDOSC Powered Without VDD Can Cause INTOSC Frequency Drift" advisory in the TMS320F2837xD Dual-Core MCUs Silicon Errata.
There is an internal 12.8-mA current source from VDD3VFL to VDD when the flash banks are active. When the flash banks are active and the device is in a low-activity state (for example, a low-power mode), this internal current source can cause VDD to rise to approximately 1.3 V. There will be zero current load to the external system VDD regulator while in this condition. This is not an issue for most regulators; however, if the system voltage regulator requires a minimum load for proper operation, then an external 82Ω resistor can be added to the board to ensure a minimal current load on VDD. See the "Low-Power Modes: Power Down Flash or Maintain Minimum Device Activity" advisory in the TMS320F2837xD Dual-Core MCUs Silicon Errata.