SPRSP14D May 2019 – February 2021 TMS320F28384D , TMS320F28384D-Q1 , TMS320F28384S , TMS320F28384S-Q1 , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S
This section explains the default boot modes, as well as all the available boot modes, supported on this device. The CPU1 boot ROM uses the boot-mode select, general-purpose input/output (GPIO) pins to determine the boot mode configuration. The CPU2 boot ROM uses the CPU1TOCPU2IPCBOOTMODE register to determine the boot mode configuration. The CM boot ROM uses the CPU1TOCMIPCBOOTMODE register to determine the boot mode configuration.
Table 8-16 lists the CPU1 boot mode options available for selection by the default boot-mode select pins. Users have the option to program the device to customize the boot modes selectable in the boot-up table as well as the boot-mode select pin GPIOs used.
All the available boot modes on the device are listed in Table 8-18.
(DEFAULT BOOT MODE SELECT PIN 1)
(DEFAULT BOOT MODE SELECT PIN 0)
|VALUE AT FLASH ENTRY POINT ADDRESS||REASON FOR VALUE||REALIZED BOOT MODE|
|0x00000000||Flash is locked/secured||Boot to Flash|
|0xFFFFFFFF||Flash is not programmed||USB Boot|
|Any other value||Flash is programmed||Boot to Flash|
The switch from flash boot mode to USB boot mode when flash is locked/secured or not programmed is only available as part of the default boot mode table on an unprogrammed device. Once a custom boot table is programmed in OTP or RAM, a selection of flash boot mode will not switch to USB boot even when the flash is unprogrammed.
|BOOT MODE||CPU SUPPORT||DETAILS|
|SCI / Wait||CPU1|
|Flash||CPU1, CPU2, CM|
|Wait||CPU1, CPU2, CM||For functional details of the boot modes, see the Boot Modes section of the TMS320F2838x Real-Time Microcontrollers Technical Reference Manual.|
|RAM||CPU1, CPU2, CM|
|SPI||CPU1||For boot table values and GPIOs for the boot modes, see Section 8.6.4.|
|Secure Flash||CPU1, CPU2, CM|
|User OTP||CPU2, CM|
|IPC Message Copy to RAM||CPU2, CM|
All the peripheral boot modes that are supported use the first instance of the peripheral module (SCIA, SPIA, I2CA, CANA, and so forth). Whenever these boot modes are referred to in this section, such as SCI boot, it is actually referring to the first module instance, which means the SCI boot on the SCIA port. The same applies to the other peripheral boots.