SPRSP14D May 2019 – February 2021 TMS320F28384D , TMS320F28384D-Q1 , TMS320F28384S , TMS320F28384S-Q1 , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S
The TMU extends the capabilities of a C28x+FPU64 by adding instructions and leveraging existing FPU instructions to speed up the execution of common trigonometric and arithmetic operations listed in Table 8-29.
|INSTRUCTIONS||C EQIVALENT OPERATION||PIPELINE CYCLES|
|MPY2PIF32/64 RaH,RbH||a = b * 2pi||2/3|
|DIV2PIF32/64 RaH,RbH||a = b / 2pi||2/3|
|DIVF32/64 RaH,RbH,RcH||a = b/c||5|
|SQRTF32/64 RaH,RbH||a = sqrt(b)||5|
|SINPUF32/64 RaH,RbH||a = sin(b*2pi)||4|
|COSPUF32/64 RaH,RbH||a = cos(b*2pi)||4|
|ATANPUF32/64 RaH,RbH||a = atan(b)/2pi||4|
|QUADF32/64 RaH,RbH,RcH,RdH||Operation to assist in calculating ATANPU2||5|
No changes have been made to existing instructions, pipeline or memory bus architecture. All TMU instructions use the existing FPU register set (R0H to R7H) to carry out their operations.