SPRSP14D May 2019 – February 2021 TMS320F28384D , TMS320F28384D-Q1 , TMS320F28384S , TMS320F28384S-Q1 , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S
Signal Pin Requirements: Before powering the device, no voltage larger than 0.3 V above VDDIO can be applied to any digital pin, and no voltage larger than 0.3 V above VDDA can be applied to any analog pin (including VREFHI).
VDDIO and VDDA Requirements: The 3.3-V supplies VDDIO and VDDA should be powered up together and kept within 0.3 V of each other during functional operation.
VDD Requirements: During the supply ramp, VDD should be kept no more than 0.3 V above VDDIO.
A single 56Ω resistor (10% tolerance) should be placed between VDD and VSS. This resistor provides a load to consume an internal VDD3VFL-to-VDD current source and avoid VDD voltage rising during low-power device conditions.