SCDS398 December   2018 TMUX6121 , TMUX6122 , TMUX6123

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Simplified Schematic
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Thermal Information
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Electrical Characteristics (Dual Supplies: ±15 V)
    6. 6.6 Switching Characteristics (Dual Supplies: ±15 V)
    7. 6.7 Electrical Characteristics (Single Supply: 12 V)
    8. 6.8 Switching Characteristics (Single Supply: 12 V)
    9. 6.9 Typical Characteristics
  7. Parameter Measurement Information
    1. 7.1 Truth Tables
  8. Detailed Description
    1. 8.1 Overview
      1. 8.1.1  On-Resistance
      2. 8.1.2  Off-Leakage Current
      3. 8.1.3  On-Leakage Current
      4. 8.1.4  Turn-On and Turn-Off Time
      5. 8.1.5  Break-Before-Make Delay
      6. 8.1.6  Charge Injection
      7. 8.1.7  Off Isolation
      8. 8.1.8  Channel-to-Channel Crosstalk
      9. 8.1.9  Bandwidth
      10. 8.1.10 THD + Noise
      11. 8.1.11 AC Power Supply Rejection Ratio (AC PSRR)
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Ultralow Leakage Current
      2. 8.3.2 Ultralow Charge Injection
      3. 8.3.3 Bidirectional and Rail-to-Rail Operation
    4. 8.4 Device Functional Modes
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Detailed Design Procedure

The TMUX6121, TMUX6122, or TMUX6123 switch is used in conjunction with the voltage holding capacitors (CH) to implement the sample and hold circuit. The basic operation is:

  1. When the switch SW2 is closed, it samples the input voltage and charges the holding capacitors (CH) to the input voltages values.
  2. When the switch SW2 is open, the holding capacitors (CH) holds its previous value, maintaining stable voltage at the amplifier output (VOUT)

Ideally, the switch delivers only the input signals to the holding capacitors. However, when the switch gets toggled, some amount of charge also gets transferred to the switch output in the form of charge injection, resulting slight sampling error. The TMUX6121, TMUX6122, and TMUX6123 switches have excellent charge injection performance of only 0.51 pC, making them ideal choices for this implementation to minimize sampling error. Due to switch and capacitor leakage current, the voltage on the hold capacitors droops with time. The TMUX6121, TMUX6122, and TMUX6123 minimize the droops due to its ultra-low leakage performance. At 25°C, the TMUX6111, TMUX6112, and TMUX6113 have extremely tiny leakage current at 0.5pA typical and 20pA max. The TMUX6121, TMUX6122, and TMUX6123 devices also support high voltage capability. The devices support up to ± 16.5 V dual supply operation, making it an ideal solution in this high voltage sample and hold application.

A second switch SW1 is also included to operate in parallel with SW2 to reduce pedestal error during switch toggling. Because both switches are driven at the same potential, they act as common-mode signal to the op-amp, thereby minimizing the charge injection effects caused by the switch toggling action. Compensation network consisting of RC and CC is also added to further reduce the pedestal error, whiling reducing the hold-time glitch and improving the settling time of the circuit.