SCDS435 September   2021 TMUX8108 , TMUX8109

ADVANCE INFORMATION  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings: TMUX810x Devices
    2. 6.2  ESD Ratings
    3. 6.3  Thermal Information: TMUX810x
    4. 6.4  Recommended Operating Conditions: TMUX810x Devices
    5. 6.5  Electrical Characteristics (Global): TMUX810x Devices
    6. 6.6  Electrical Characteristics (±36-V Dual Supply)
    7. 6.7  Electrical Characteristics (72-V Single Supply)
    8. 6.8  Electrical Characteristics (100-V Single Supply)
    9. 6.9  Switching Characteristics: TMUX810x Devices
    10. 6.10 Typical Characteristics
  7. Parameter Measurement Information
    1. 7.1  Truth Tables
    2. 7.2  On-Resistance
    3. 7.3  Off-Leakage Current
    4. 7.4  On-Leakage Current
    5. 7.5  Break-Before-Make Delay
    6. 7.6  Enable Delay Time
      1. 7.6.1 Device Turn On Time
    7. 7.7  Transition Time
    8. 7.8  Charge Injection
    9. 7.9  Off Isolation
    10. 7.10 Crosstalk
    11. 7.11 Bandwidth
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Flat On - Resistance
      2. 8.3.2 Protection Features
        1. 8.3.2.1 Fail-Safe Logic
        2. 8.3.2.2 Latch-up Immunity
      3. 8.3.3 Bidirectional Operation
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Pin Configuration and Functions

GUID-45892D94-3FAD-4DC0-A66A-CD70364AA557-low.gifFigure 5-1 PW Package16-Pin TSSOP Top View
GUID-37F66FC0-44FE-49FF-A567-7FAE1F91525D-low.gifFigure 5-2 RUM Package16-Pin WQFNTop View
Table 5-1 Pin Functions: TMUX8108
PIN TYPE(1) DESCRIPTION
NAME TSSOP WQFN
A0 1 15 I Logic control input address 0 (A0).
EN 2 16 I Active high digital enable (EN) pin. The device is disabled and all switches become high impedance when the pin is low. When the pin is high, the Ax logic inputs determine individual switch states.
VSS 3 1 P Negative power supply. This pin is the most negative power-supply potential. In single-supply applications, this pin can be connected to ground. For reliable operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VSS and GND.
S1 4 2 I/O Source pin 1. Can be an input or output.
S2 5 3 I/O Source pin 2. Can be an input or output.
S3 6 4 I/O Source pin 3. Can be an input or output.
S4 7 5 I/O Source pin 4. Can be an input or output.
D 8 6 I/O Drain pin. Can be an input or output.
S8 9 7 I/O Source pin 8. Can be an input or output.
S7 10 8 I/O Source pin 7. Can be an input or output.
S6 11 9 I/O Source pin 6. Can be an input or output.
S5 12 10 I/O Source pin 5. Can be an input or output.
VDD 13 11 P Positive power supply. This pin is the most positive power-supply potential. For reliable operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and GND.
GND 14 12 P Ground (0 V) reference
A2 15 13 I Logic control input address 2 (A2).
A1 16 14 I Logic control input address 1 (A1).
I = input, O = output, I/O = input and output, P = power
GUID-9327CA30-859F-4F87-BB1A-DDD41F916120-low.gifFigure 5-3 PW Package16-Pin TSSOPTop View
GUID-5F8702B1-0ED7-4449-BB1C-00260CC4B7F2-low.gifFigure 5-4 RUM Package16-Pin WQFNTop View
Table 5-2 Pin Functions: TMUX8109
PIN TYPE(1) DESCRIPTION
NAME TSSOP WQFN
A0 1 15 I Logic control input address 0 (A0).
EN 2 16 I Active high digital enable (EN) pin. The device is disabled and all switches become high impedance when the pin is low. When the pin is high, the Ax logic inputs determine individual switch states.
VSS 3 1 P Negative power supply. This pin is the most negative power-supply potential. In single-supply applications, this pin can be connected to ground. For reliable operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VSS and GND.
S1A 4 2 I/O Source pin 1A. Can be an input or output.
S2A 5 3 I/O Source pin 2A. Can be an input or output.
S3A 6 4 I/O Source pin 3A. Can be an input or output.
S4A 7 5 I/O Source pin 4A. Can be an input or output.
DA 8 6 I/O Drain terminal A. Can be an input or output.
DB 9 7 I/O Drain terminal B. Can be an input or output.
S4B 10 8 I/O Source pin 4B. Can be an input or output.
S3B 11 9 I/O Source pin 3B. Can be an input or output.
S2B 12 10 I/O Source pin 2B. Can be an input or output.
S1B 13 11 I/O Source pin 1B. Can be an input or output.
VDD 14 12 P Positive power supply. This pin is the most positive power-supply potential. For reliable operation, connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and GND.
GND 15 13 P Ground (0 V) reference
A1 16 14 I Logic control input address 1 (A1).