SLASEW5 December   2020 TMUXHS4412

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 High-Speed Performance Parameters
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Output Enable and Power Savings
      2. 7.3.2 Data Line Biasing
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 PCIe Lane Muxing
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Pin-to-pin Passive versus Redriver Option
        4. 8.2.1.4 Application Curves
    3. 8.3 Systems Examples
      1. 8.3.1 PCIe Muxing for Hybrid SSD
      2. 8.3.2 DisplayPort Main Link
      3. 8.3.3 USB 4.0 / TBT 3.0 Demuxing
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.1.1 Design Requirements

Table 8-1 provide various parameters and their expected values to implement the PCIe lane switching topology. Note the recommendation is for illustration purpose only.
Table 8-1 Design Parameters
DESIGN PARAMETER VALUE

(VCC = 3.3 V)

 VALUE

(VCC = 1.8 V)
Dx[P/N], DAx[P/N], DBx[P/N] CM input voltage 0 V to 1.8 V 0 V to 0.9V

Must be biased from Dx[P/N] side)
SEL/PD pin max voltage for low <0.25*VCC
SEL/PD pin min voltage for high >0.75*VCC
AC coupling capacitor for PCIe TX pins 75 nF to 265 nF
Decoupling capacitor for VCC 0.1 uF