SLOS649B March   2010  – May 2016 TPA2026D2

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 I2C Timing Requirements
    7. 7.7 Dissipation Ratings
    8. 7.8 Operating Characteristics
    9. 7.9 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Automatic Gain Control
        1. 9.3.1.1 Fixed Gain
        2. 9.3.1.2 Limiter Level
        3. 9.3.1.3 Compression Ratio
        4. 9.3.1.4 Interaction Between Compression Ratio and Limiter Range
        5. 9.3.1.5 Noise Gate Threshold
        6. 9.3.1.6 Maximum Gain
        7. 9.3.1.7 Attack, Release, and Hold Time
      2. 9.3.2 Operation With DACS and CODECS
      3. 9.3.3 Short-Circuit Auto-Recovery
      4. 9.3.4 Filter-Free Operation and Ferrite Bead Filters
    4. 9.4 Device Functional Modes
      1. 9.4.1 TPA2026D2 AGC Operation
        1. 9.4.1.1 AGC Start-Up Condition
      2. 9.4.2 TPA2026D2 AGC Recommended Settings
    5. 9.5 Programming
      1. 9.5.1 General I2C Operation
      2. 9.5.2 Single and Multiple-Byte Transfers
      3. 9.5.3 Single-Byte Write
      4. 9.5.4 Multiple-Byte Write and Incremental Multiple-Byte Write
      5. 9.5.5 Single-Byte Read
      6. 9.5.6 Multiple-Byte Read
    6. 9.6 Register Maps
      1. 9.6.1 IC Function Control (Address: 1)
      2. 9.6.2 AGC Attack Control (Address: 2)
      3. 9.6.3 AGC Release Control (Address: 3)
      4. 9.6.4 AGC Hold Time Control (Address: 4)
      5. 9.6.5 AGC Fixed Gain Control (Address: 5)
      6. 9.6.6 AGC Control (Address: 6)
      7. 9.6.7 AGC Control (Address: 7)
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 TPA2026D2 With Differential Input Signals
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 Surface Mount Capacitor
          2. 10.2.1.2.2 Decoupling Capacitor, CS
          3. 10.2.1.2.3 Input Capacitors, CI
        3. 10.2.1.3 Application Curves
      2. 10.2.2 TPA2026D2 With Single-Ended Input Signal
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
        3. 10.2.2.3 Application Curves
  11. 11Power Supply Recommendations
    1. 11.1 Power Supply Decoupling Capacitors
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Pad Size
      2. 12.1.2 Component Location
      3. 12.1.3 Trace Width
    2. 12.2 Layout Example
    3. 12.3 Efficiency and Thermal Considerations
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
    2. 13.2 Community Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information
    1. 14.1 YZH Package Dimensions

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • Fast AGC Start-Up Time: 5 ms
  • Pinout Compatible With TPA2016D2
  • Filter-Free Class-D Architecture
  • 3.2 W/Ch Into 4 Ω at 5 V (10% THD+N)
  • 750 mW/Ch Into 8 Ω at 3.6 V (10% THD+N)
  • Power Supply Range: 2.5 V to 5.5 V
  • Flexible Operation With or Without I2C
  • Programmable DRC and AGC Parameters
  • Digital I2C Volume Control
  • Selectable Gain from 0 dB to 30 dB in 1-dB Steps
  • Selectable Attack, Release, and Hold Times
  • 4 Selectable Compression Ratios
  • Low Supply Current: 3.5 mA
  • Low Shutdown Current: 0.2 μA
  • High PSRR: 80 dB
  • AGC Enable or Disable Function
  • Limiter Enable or Disable Function
  • Short-Circuit and Thermal Protection
  • Space-Saving Package
    • 2.2 mm × 2.2 mm Nano-Free™ DSBGA (YZH)

2 Applications

  • Wireless or Cellular Handsets and PDAs
  • Portable Navigation Devices
  • Portable DVD Players
  • Notebook PCs
  • Portable Radios
  • Portable Games
  • Educational Toys
  • USB Speakers

3 Description

The TPA2026D2 device is a stereo, filter-free Class-D audio power amplifier with volume control, dynamic range compression (DRC), and automatic gain control (AGC). It is available in a 2.2 mm × 2.2 mm DSBGA package.

The DRC and AGC function in the TPA2026D2 is programmable through a digital I2C interface. The DRC and AGC function can be configured to automatically prevent distortion of the audio signal and enhance quiet passages that are normally not heard. The DRC and AGC can also be configured to protect the speaker from damage at high power levels and compress the dynamic range of music to fit within the dynamic range of the speaker. The gain can be selected from 0 dB to +30 dB in 1-dB steps. The TPA2026D2 is capable of driving 3.2 W/Ch at 5 V into an 4-Ω load or 750 mW/Ch at 3.6 V into an 8-Ω load. The device features independent software shutdown controls for each channel and also provides thermal and short-circuit protection. The TPA2026D2 has faster AGC gain ramp during start-up than TPA2016D2.

In addition to these features, a fast start-up time and small package size make the TPA2026D2 an ideal choice for cellular handsets, PDAs, and other portable applications.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
TPA2026D2 DSBGA (16) 2.20 mm × 2.20 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Simplified Application Diagram

TPA2026D2 sys_app_dia3_los624.gif

4 Revision History

Changes from A Revision (January 2011) to B Revision

  • Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section.Go

Changes from * Revision (March 2010) to A Revision

  • Changed the Default values in Table 5 Go
  • Changed the Default value of the IC Function Control Table (I2C BIT 0) From: 0 (disabled) To: 1 (enabled) Go