SLOS649B March   2010  – May 2016 TPA2026D2

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 I2C Timing Requirements
    7. 7.7 Dissipation Ratings
    8. 7.8 Operating Characteristics
    9. 7.9 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Automatic Gain Control
        1. 9.3.1.1 Fixed Gain
        2. 9.3.1.2 Limiter Level
        3. 9.3.1.3 Compression Ratio
        4. 9.3.1.4 Interaction Between Compression Ratio and Limiter Range
        5. 9.3.1.5 Noise Gate Threshold
        6. 9.3.1.6 Maximum Gain
        7. 9.3.1.7 Attack, Release, and Hold Time
      2. 9.3.2 Operation With DACS and CODECS
      3. 9.3.3 Short-Circuit Auto-Recovery
      4. 9.3.4 Filter-Free Operation and Ferrite Bead Filters
    4. 9.4 Device Functional Modes
      1. 9.4.1 TPA2026D2 AGC Operation
        1. 9.4.1.1 AGC Start-Up Condition
      2. 9.4.2 TPA2026D2 AGC Recommended Settings
    5. 9.5 Programming
      1. 9.5.1 General I2C Operation
      2. 9.5.2 Single and Multiple-Byte Transfers
      3. 9.5.3 Single-Byte Write
      4. 9.5.4 Multiple-Byte Write and Incremental Multiple-Byte Write
      5. 9.5.5 Single-Byte Read
      6. 9.5.6 Multiple-Byte Read
    6. 9.6 Register Maps
      1. 9.6.1 IC Function Control (Address: 1)
      2. 9.6.2 AGC Attack Control (Address: 2)
      3. 9.6.3 AGC Release Control (Address: 3)
      4. 9.6.4 AGC Hold Time Control (Address: 4)
      5. 9.6.5 AGC Fixed Gain Control (Address: 5)
      6. 9.6.6 AGC Control (Address: 6)
      7. 9.6.7 AGC Control (Address: 7)
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 TPA2026D2 With Differential Input Signals
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 Surface Mount Capacitor
          2. 10.2.1.2.2 Decoupling Capacitor, CS
          3. 10.2.1.2.3 Input Capacitors, CI
        3. 10.2.1.3 Application Curves
      2. 10.2.2 TPA2026D2 With Single-Ended Input Signal
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
        3. 10.2.2.3 Application Curves
  11. 11Power Supply Recommendations
    1. 11.1 Power Supply Decoupling Capacitors
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Pad Size
      2. 12.1.2 Component Location
      3. 12.1.3 Trace Width
    2. 12.2 Layout Example
    3. 12.3 Efficiency and Thermal Considerations
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
    2. 13.2 Community Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information
    1. 14.1 YZH Package Dimensions

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Specifications

7.1 Absolute Maximum Ratings(1)

over operating free-air temperature range (unless otherwise noted).
MIN MAX UNIT
VDD Supply voltage AVDD, PVDDR, PVDDL –0.3 6 V
Input voltage SDZ, INR+, INR–, INL+, INL– –0.3 VDD + 0.3 V
SDA, SCL –0.3 6
Continuous total power dissipation See Dissipation Ratings
RL Minimum load resistance 3.2 Ω
TA Operating free-air temperature –40 85 °C
TJ Operating junction temperature –40 150 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

MIN MAX UNIT
VDD Supply voltage AVDD, PVDDR, PVDDL 2.5 5.5 V
VIH High-level input voltage SDZ, SDA, SCL 1.3 V
VIL Low-level input voltage SDZ, SDA, SCL 0.6 V
TA Operating free-air temperature –40 +85 °C

7.4 Thermal Information

THERMAL METRIC(1) TPA2026D2 UNIT
YZH (DSBGA)
16 PINS
RθJA Junction-to-ambient thermal resistance 71 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 0.4 °C/W
RθJB Junction-to-board thermal resistance 14.4 °C/W
ψJT Junction-to-top characterization parameter 1.9 °C/W
ψJB Junction-to-board characterization parameter 13.6 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance — °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

at TA = 25°C, VDD = 3.6 V, SDZ = 1.3 V, and RL = 8 Ω + 33 μH (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VDD Supply voltage range 2.5 3.6 5.5 V
ISDZ Shutdown quiescent current SDZ = 0.35 V, VDD = 2.5 V 0.1 1 µA
SDZ = 0.35 V, VDD = 3.6 V 0.2 1
SDZ = 0.35 V, VDD = 5.5 V 0.3 1
ISWS Software shutdown quiescent current SDZ = 1.3 V, VDD = 2.5 V 35 50 µA
SDZ = 1.3 V, VDD = 3.6 V 50 70
SDZ = 1.3 V, VDD = 5.5 V 75 110
IDD Supply current VDD = 2.5 V 3.5 4.5 mA
VDD = 3.6 V 3.7 4.7
VDD = 5.5 V 4.5 5.5
fSW Class-D switching frequency 275 300 325 kHz
IIH High-level input current VDD = 5.5 V, SDZ = 5.8 V 1 µA
IIL Low-level input current VDD = 5.5 V, SDZ = –0.3 V –1 µA
tSTART Start-up time 2.5 V ≤ VDD ≤ 5.5 V no pop, CIN ≤ 1 μF 5 ms
POR Power on reset ON threshold 2 2.3 V
POR Power on reset hysteresis 0.2 V
CMRR Input common-mode rejection RL = 8 Ω, Vicm = 0.5 V and Vicm = VDD – 0.8 V,
differential inputs shorted		 –70 dB
Voo Output offset voltage VDD = 3.6 V, AV = 6 dB, RL = 8 Ω, inputs AC grounded 2 10 mV
ZOUT Output impedance in shutdown mode SDZ = 0.35 V 2 kΩ
Gain accuracy Compression and limiter disabled, Gain = 0 to 30 dB –0.5 0.5 dB
PSRR Power supply rejection ratio VDD = 2.5 V to 4.7 V –80 dB

7.6 I2C Timing Requirements

For I2C Interface Signals Over Recommended Operating Conditions (unless otherwise noted)
MIN TYP MAX UNIT
fSCL Frequency, SCL No wait states 400 kHz
tW(H) Pulse duration, SCL high 0.6 μs
tW(L) Pulse duration, SCL low 1.3 μs
tSU(1) Setup time, SDA to SCL 100 ns
th1 Hold time, SCL to SDA 10 ns
t(buf) Bus free time between stop and start condition 1.3 μs
tSU2 Setup time, SCL to start condition 0.6 μs
th2 Hold time, start condition to SCL 0.6 μs
tSU3 Setup time, SCL to stop condition 0.6 μs

7.7 Dissipation Ratings

PACKAGE TA ≤ 25°C DERATING FACTOR TA = 70°C TA = 85°C
16-ball WCSP(1) 1.25 W 10 mW/°C 0.8 W 0.65 W
(1) Dissipations ratings are for a 2-side, 2-plane PCB.

7.8 Operating Characteristics

at TA = 25°C, VDD = 3.6V, SDZ = 1.3 V, RL = 8 Ω +33 μH, and AV = 6 dB (unless otherwise noted).
MIN TYP MAX UNIT
kSVR Power-supply ripple rejection ratio VDD = 3.6 Vdc with AC of 200 mVPP at 217 Hz –68 dB
THD+N Total harmonic distortion + noise faud_in = 1 kHz, PO = 550 mW, VDD = 3.6 V 0.1%
faud_in = 1 kHz, PO = 1 W, VDD = 5 V 0.1%
faud_in = 1 kHz, PO = 630 mW, VDD = 3.6 V 1%
faud_in = 1 kHz, PO = 1.4 W, VDD = 5 V 1%
NfonF Output integrated noise Av = 6 dB 44 μV
NfoA Output integrated noise Av = 6 dB floor, A-weighted 33 μV
FR Frequency response Av = 6 dB 20 20000 Hz
Pomax Maximum output power THD+N = 10%, VDD = 5 V, RL = 8 Ω 1.72 W
THD+N = 10%, VDD = 3.6 V, RL = 8 Ω 750 mW
THD+N = 1%, VDD = 5 V, RL = 8 Ω 1.4 W
THD+N = 1% , VDD = 3.6 V, RL = 8 Ω 630 mW
η Efficiency THD+N = 1%, VDD = 3.6 V, RL = 8 Ω, PO= 0.63 W 90%
THD+N = 1%, VDD = 5 V, RL = 8 Ω, PO = 1.4 W 90%
TPA2026D2 scl_tim_los492.gif Figure 1. SCL and SDA Timing
TPA2026D2 st_stop_los524.gif Figure 2. Start and Stop Conditions Timing

7.9 Typical Characteristics

with C(DECOUPLE) = 1 μF, CI = 1 µF. All THD + N graphs are taken with outputs out of phase (unless otherwise noted). All data is taken on left channel.

Table 1. Table of Graphs

FIGURE
Quiescent supply current vs Supply voltage Figure 3
Supply current vs Supply voltage in shutdown Figure 4
Output level vs Input level Figure 5
Output level vs Input level Figure 6
Output level vs Input level Figure 7
Output level vs Input level Figure 8
Output level vs Input level Figure 9
Supply ripple rejection ratio vs Frequency, 8 Ω Figure 10
Total harmonic distortion + noise vs Frequency VSUPPLY = 2.5 V, 4 Ω Figure 11
Total harmonic distortion + noise vs Frequency VSUPPLY = 2.5 V, 8 Ω Figure 12
Total harmonic distortion + noise vs Frequency VSUPPLY = 3.6 V, 4 Ω Figure 13
Total harmonic distortion + noise vs Frequency VSUPPLY = 3.6 V, 8 Ω Figure 14
Total harmonic distortion + noise vs Frequency VSUPPLY = 5 V, 4 Ω Figure 15
Total harmonic distortion + noise vs Frequency VSUPPLY = 5 V, 8 Ω Figure 16
Total harmonic distortion + noise vs Output power, 4 Ω Figure 17
Total harmonic distortion + noise vs Output power, 8 Ω Figure 18
Efficiency vs Output power (per channel), 4 Ω Figure 19
Efficiency vs Output power (per channel), 8 Ω Figure 20
Total power dissipation vs Total output power, 4 Ω Figure 21
Total power dissipation vs Total output power, 8 Ω Figure 22
Total supply current vs Total output power, 4 Ω Figure 23
Total supply current vs Total output power, 8 Ω Figure 24
Output power vs Supply voltage, 4 Ω Figure 25
Output power vs Supply voltage, 8 Ω Figure 26
TPA2026D2 vs TPA2016D2 Start-up gain ramp Figure 27
TPA2026D2 vs TPA2016D2 Shutdown gain ramp Figure 28
Shutdown time Figure 29
Start-up time Figure 30
TPA2026D2 g001_los524.gif Figure 3. Quiescent Supply Current vs Supply Voltage
TPA2026D2 g003_los524.gif Figure 5. Output Level vs Input level With Limiter Enabled
TPA2026D2 g005_los524.gif Figure 7. Output Level vs Input level With 4:1 Compression
TPA2026D2 g007_los524.gif Figure 9. Output Level vs Input level
TPA2026D2 G009_LOS649.gif Figure 11. Total Harmonic Distortion + Noise vs Frequency VSUPPLY = 2.5 V, 4 Ω
TPA2026D2 G011_LOS649.gif Figure 13. Total Harmonic Distortion + Noise vs Frequency VSUPPLY = 3.6 V, 4 Ω
TPA2026D2 G013_LOS649.gif Figure 15. Total Harmonic Distortion + Noise vs Frequency VSUPPLY = 5 V, 4 Ω
TPA2026D2 G015_LOS649.gif Figure 17. Total Harmonic Distortion + Noise vs Power,
4 Ω
TPA2026D2 G017_LOS649.gif Figure 19. Efficiency vs Output Power (Per Channel), 4 Ω
TPA2026D2 G019_LOS649.gif Figure 21. Total Power Dissipation vs Total Output Power,
4 Ω
TPA2026D2 G021_LOS649.gif Figure 23. Total Supply Current vs Total Output Power, 4 Ω
TPA2026D2 G023_LOS649.gif Figure 25. Output Power vs Supply Voltage, 4 Ω
TPA2026D2 G025_LOS649.png Figure 27. TPA2026D2 vs TPA2016D2 Start-Up Gain Ramp
TPA2026D2 volt_time1_los488.gif Figure 29. Shutdown Time
TPA2026D2 g002_los524.gif Figure 4. Supply Current Vs Supply Voltage in Shutdown
TPA2026D2 g004_los524.gif Figure 6. Output Level vs Input level With 2:1 Compression
TPA2026D2 g006_los524.gif Figure 8. Output Level vs Input level With 8:1 Compression
TPA2026D2 G008_LOS649.gif Figure 10. Supply Ripple Rejection Ratio vs Frequency, 8 Ω
TPA2026D2 G012_LOS649.gif Figure 12. Total Harmonic Distortion + Noise vs Frequency VSUPPLY = 2.5 V, 8 Ω
TPA2026D2 G010_LOS649.gif Figure 14. Total Harmonic Distortion + Noise Vs Frequency VSUPPLY = 3.6 V, 8 Ω
TPA2026D2 G014_LOS649.gif Figure 16. Total Harmonic Distortion + Noise vs Frequency VSUPPLY = 5 V, 8 Ω
TPA2026D2 G016_LOS649.gif Figure 18. Total Harmonic Distortion + Noise vs Power,
8 Ω
TPA2026D2 G018_LOS649.gif Figure 20. Efficiency vs Output Power (Per Channel), 8 Ω
TPA2026D2 G020_LOS649.gif Figure 22. Total Power Dissipation vs Total Output Power,
8 Ω
TPA2026D2 G022_LOS649.gif Figure 24. Total Supply Current vs Total Output Power, 8 Ω
TPA2026D2 G024_LOS649.gif Figure 26. Output Power vs Supply Voltage, 8 Ω
TPA2026D2 G026_LOS649.png Figure 28. TPA2026D2 vs TPA2016D2 Shutdown Gain Ramp
TPA2026D2 volt_time2_los488.gif Figure 30. Start-Up Time