SLOS528F July   2009  – April 2017 TPA3110D2

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and F unctions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 DC Characteristics: 24 V
    6. 7.6 DC Characteristics: 12 V
    7. 7.7 AC Characteristics: 24 V
    8. 7.8 AC Characteristics: 12 V
    9. 7.9 Typical Characteristics
  8. Parameter Measurement Information
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 TPA3110D2 Modulation Scheme
        1. 9.3.1.1 Ferrite Bead Filter Considerations
        2. 9.3.1.2 Efficiency: LC Filter Required With The Traditional Class-D Modulation Scheme
        3. 9.3.1.3 When to Use an Output Filter for EMI Suppression
      2. 9.3.2 Gain Setting Via GAIN0 And GAIN1 Inputs
      3. 9.3.3 Differential Inputs
      4. 9.3.4 PLIMIT
      5. 9.3.5 GVDD Supply
      6. 9.3.6 PBTL Select
      7. 9.3.7 Thermal Protection
      8. 9.3.8 DC Detect
      9. 9.3.9 Short-Circuit Protection and Automatic Recovery Feature
    4. 9.4 Device Functional Modes
      1. 9.4.1 SD Operation
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Stereo Class-D Amplifier With BTL Output and Single-Ended Inputs With Power Limiting
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 Input Resistance
          2. 10.2.1.2.2 Input Capacitor, CI
          3. 10.2.1.2.3 BSN and BSP Capacitors
          4. 10.2.1.2.4 Using Low-ESR Capacitors
        3. 10.2.1.3 Application Curves
      2. 10.2.2 Stereo Class-D Amplifier With PBTL Output and Single-Ended Input
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
        3. 10.2.2.3 Application Curve
  11. 11Power Supply Recommendations
    1. 11.1 Power Supply Decoupling, CS
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Development Support
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Community Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Pin Configuration and F unctions

PWP Package
28-Pin HTSSOP With PowerPAD™
Top View
TPA3110D2 PinOut_los528.gif

Table 1. Pin Functions

PIN TYPE DESCRIPTION
NO. NAME
1 SD I Shutdown logic input for audio amp (LOW = outputs Hi-Z, HIGH = outputs enabled). TTL logic levels with compliance to AVCC.
2 FAULT O Open drain output used to display short circuit or dc detect fault status. Voltage compliant to AVCC. Short circuit faults can be set to auto-recovery by connecting FAULT pin to SD pin. Otherwise, both short circuit faults and dc detect faults must be reset by cycling PVCC.
3 LINP I Positive audio input for left channel. Biased at 3 V.
4 LINN I Negative audio input for left channel. Biased at 3 V.
5 GAIN0 I Gain select least significant bit. TTL logic levels with compliance to AVCC.
6 GAIN1 I Gain select most significant bit. TTL logic levels with compliance to AVCC.
7 AVCC P Analog supply
8 AGND Analog signal ground. Connect to the thermal pad.
9 GVDD O High-side FET gate drive supply. Nominal voltage is 7V. Also should be used as supply for PLIMIT function.
10 PLIMIT I Power limit level adjust. Connect a resistor divider from GVDD to GND to set power limit. Connect directly to GVDD for no power limit.
11 RINN I Negative audio input for right channel. Biased at 3 V.
12 RINP I Positive audio input for right channel. Biased at 3 V.
13 NC Not connected
14 PBTL I Parallel BTL mode switch
15 PVCCR P Power supply for right channel H-bridge. Right channel and left channel power supply inputs are connect internally.
16 PVCCR P Power supply for right channel H-bridge. Right channel and left channel power supply inputs are connect internally.
17 BSPR I Bootstrap I/O for right channel, positive high-side FET.
18 OUTPR O Class-D H-bridge positive output for right channel.
19 PGND Power ground for the H-bridges.
20 OUTNR O Class-D H-bridge negative output for right channel.
21 BSNR I Bootstrap I/O for right channel, negative high-side FET.
22 BSNL I Bootstrap I/O for left channel, negative high-side FET.
23 OUTNL O Class-D H-bridge negative output for left channel.
24 PGND Power ground for the H-bridges.
25 OUTPL O Class-D H-bridge positive output for left channel.
26 BSPL I Bootstrap I/O for left channel, positive high-side FET.
27 PVCCL P Power supply for left channel H-bridge. Right channel and left channel power supply inputs are connect internally.
28 PVCCL P Power supply for left channel H-bridge. Right channel and left channel power supply inputs are connect internally.