SLVSIM2A June   2025  – August 2025 TPD4S480-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings—JEDEC Specification
    3. 5.3 ESD Ratings—IEC Specification
    4. 5.4 ESD Ratings—ISO Specification
    5. 5.5 Recommended Operating Conditions
    6. 5.6 Thermal Information
    7. 5.7 Electrical Characteristics
    8. 5.8 Timing Requirements
    9. 5.9 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 4-Channels of Short-to-VBUS Overvoltage Protection (CC1, CC2, SBU1, SBU2 Pins or CC1, CC2, DP, DM Pins): 63VDC Tolerant
      2. 6.3.2 4-Channels of IEC 61000-4-2 ESD Protection (CC1, CC2, SBU1, SBU2 Pins)
      3. 6.3.3 CC1, CC2 Overvoltage Protection FETs 600-mA Capable for Passing VCONN Power
      4. 6.3.4 CC Dead Battery Resistors Integrated for Handling the Dead Battery Use Case in Mobile Devices
      5. 6.3.5 EPR Adapter
        1. 6.3.5.1 VBUS Divider
        2. 6.3.5.2 EPR Blocking FET Gate Driver
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
    3. 7.3 Design Requirements
      1. 7.3.1 EPR Design Requirements
    4. 7.4 Detailed Design Procedure
      1. 7.4.1 VBIAS Capacitor Selection
      2. 7.4.2 CC Line Capacitance
      3. 7.4.3 FLT Pin Operation
      4. 7.4.4 Dead Battery Operation
    5. 7.5 Application Curves
    6. 7.6 Power Supply Recommendations
    7. 7.7 Layout
      1. 7.7.1 Layout Guidelines
      2. 7.7.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VI Input voltage EPR_EN -0.3 3.6 V
VI Input voltage VPWR -0.3 5 V
RPD_G1, RPD_G2 -0.3 63 V
VI Input voltage VBUS (VPWR = 0V) -0.3 24 V
VI Input voltage VBUS (VPWR > 2.7V) -0.3 63 V
VO Output voltage FLT -0.3 6 V
VBIAS -0.3 63 V
VO Output voltage VBUS_LV -0.3 24 V
VO Output voltage EPR_BLK_G -0.3 30 V
VIO I/O voltage CC1, CC2, SBU1, SBU2 -0.3 6 V
C_CC1, C_CC2, C_SBU1, C_SBU2 -0.3 63 V
trise Input voltage rise time (VI > 36V) CC1, CC2, SBU1, SBU2 400 ns
TJ Operating junction temperature -40 125 °C
Tstg Storage temperature -65 150 °C
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.