SLVSEE0D February   2018  – September 2021

PRODUCTION DATA

1. Features
2. Applications
3. Description
4. Revision History
5. Pin Configuration and Functions
6. Specifications
7. Detailed Description
1. 7.1 Overview
2. 7.2 Functional Block Diagram
3. 7.3 Feature Description
1. 7.3.1 Current limit
2. 7.3.2 DELAY Pin Configuration
3. 7.3.3 Stand-alone Operation
4. 7.3.4 Fault Truth Table
5. 7.3.5 Full Diagnostics
1. 7.3.5.1 Short-to-GND and Overload Detection
3. 7.3.5.3 Short-to-Battery Detection
4. 7.3.5.4 Thermal Fault Detection
6. 7.3.6 Full Protections
4. 7.4 Device Functional Modes
1. 7.4.1 Working Modes
8. Application and Implementation
1. 8.1 Application Information
2. 8.2 Typical Application
9. Power Supply Recommendations
10. 10Layout
11. 11Device and Documentation Support
12. 12Mechanical, Packaging, and Orderable Information

• DGN|8
• DGN|8

### 7.3.1 Current limit

A high-accuracy current limit allows high reliability of the design. The current limit protects the load and the power supply from overstressing during short-circuit-to-GND or power-up conditions. The current limit can also save system cost by reducing the size of PCB traces and connectors, and the capacity of the preceding power stage.

When a current limit threshold is hit, a closed loop immediately activates. The output current is clamped at the set value, and a fault is reported. The device heats up because of high power dissipation on the power FET.

The device has two current limit thresholds.

• Internal current limit: The internal current limit is fixed at ICL(int). Tie the CL pin directly to the device GND for large-transient-current applications.

• External adjustable current limit: An external resistor is used to set the current limit threshold. Use Equation 1 to calculate R(CL). The external adjustable current limit allows the flexibility to set the current limit value by application.

Equation 1.

where

• VCL(th) is the internal band-gap voltage.
• K(CL) is the ratio of the output current and the current limit set value.
• K(CL) is constant across temperature and supply voltage.
Note:

When a GND network is used, that causes a level shift between the device GND and board GND, so the CL pin must be connected to the device GND.

For better protection from a hard short-to-GND condition (when the IN pin is enabled, a short-to-GND occurs suddenly), the device will implement a fast-trip protection to turn off the output before the current limit closed loop is set up. Typically, the fast-trip response time is less than 1 µs. With a fast response like this, the device can achieve a better inrush current-suppression performance.

Figure 7-1 Current Limit