SLVSFI1A July   2021  – December 2021 TPS1HC100-Q1

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
    1. 5.1 Recommended Connections for Unused Pins
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SNS Timing Characteristics
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Accurate Current Sense
      2. 8.3.2 Programmable Current Limit
        1. 8.3.2.1 Capacitive Charging
      3. 8.3.3 Inductive-Load Switching-Off Clamp
      4. 8.3.4 Full Protections and Diagnostics
        1. 8.3.4.1  Short-Circuit and Overload Protection
        2. 8.3.4.2  Open-Load and Short-to-Battery Detection
        3. 8.3.4.3  Short-to-Battery Detection
        4. 8.3.4.4  Reverse-Polarity and Battery Protection
        5. 8.3.4.5  Latch-Off Mode
        6. 8.3.4.6  Thermal Protection Behavior
        7. 8.3.4.7  UVLO Protection
        8. 8.3.4.8  Loss of GND Protection
        9. 8.3.4.9  Loss of Power Supply Protection
        10. 8.3.4.10 Reverse Current Protection
        11. 8.3.4.11 Protection for MCU I/Os
      5. 8.3.5 Diagnostic Enable Function
    4. 8.4 Device Functional Modes
      1. 8.4.1 Working Mode
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Dynamically Changing Current Limit
        2. 9.2.2.2 AEC Q100-012 Test Grade A Certification
        3. 9.2.2.3 EMC Transient Disturbances Test
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
      1. 11.2.1 Without a GND Network
      2. 11.2.2 With a GND Network
    3. 11.3 Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Programmable Current Limit

A high-accuracy current limit allows higher reliability, which protects the power supply during short circuit or power up. Also, a current limit can save system costs by reducing PCB traces, connector size, and the capacity of the preceding power stage.

Current limiting offers protection from over-stressing to the load and integrated power FET. The current limit regulates the output current to the set value, and pulls up the SNS pin to VSNSFH and asserts the FLT pin as diagnostic reports. The three current-limit thresholds are:

  • External programmable current limit – an external resistor, RILIM, is used to set the channel current limit. When the current through the device exceeds ICL (current limit threshold), a closed loop steps in immediately. VGS voltage regulates accordingly, leading to the VDS voltage regulation. When the closed loop is set up, the current is clamped at the set value. The external programmable current limit provides the capability to set the current-limit value by application.

    Additionally, this value can be dynamically changed by changing the resistance on the ILIM pin. This information can be seen in the Applications section.

  • Internal current limit: ILIM pin shorted to ground – if the external current limit is out of range on the lower end or the ILIM pin is shorted to ground, the internal current limit is fixed and typically 7 A. To use the internal current limit for large-current applications, tie the ILIM pin directly to the device GND.
  • Internal current limit: ILIM pin open – if the external resistor is out of range on the higher end or the ILIM pin is open, the current limit reverts to 3 A or half the current limit range. This level is still above the nominal operation for the device to operate in DC steady state but is low enough that if a pin fault occurs and the RILIM opens up, the current does not default to the highest rating and put additional stress on the power supply.

Both the internal current limit (Ilim,nom) and external programmable current limit are always active when VBB is powered and EN is high. The lower value one (of ILIM and the external programmable current limit) is applied as the actual current limit. The typical deglitch time for the current limit to assert is 2.5 µs.

Note that if a GND network is used (which leads to the level shift between the device GND and board GND), the ILIM pin must be connected with device GND. Calculate RILIM with Equation 2.

Equation 2. RILIM = KCL / ILIM

For better protection from a hot short condition (when VBB is high, channel is on, and a short to GND happens suddenly), an over current protection, OVCR, circuit is triggered that makes sure to limit the maximum current the device allows to go through. With this OVCR, the device is protected during hot short events.

For more information about the current limiting feature, see the Short-Circuit and Overload Protection section.

Current Limit Accuracy

The TPS1HC100-Q1 has very tight accuracy of the current limit regulation level across the full range of currents and temperature. This accuracy is defined at several defined RILIM values, 7.15 kΩ, 25 kΩ, and 71.5 kΩ specified in the Electrical Characteristics. As the current limit is changed with the RILIM, the KCL ratio value also slightly changes. Additionally, the current limit architecture in the device allows for the tightest variation at current limit set by a 25-kΩ RILIM, 1.9 A, of +18%, -7% and at the lower and upper ends of the range, 690 mA and 6.15 A respectively, to be about ±25%. Then, using the boundaries for RILIM of 7.15 kΩ and 71.5 kΩ, a graph can be built to linearly interpret the error for RILIM values that are inside of the range. This graph can be seen in the figure below.

Figure 8-4 Current Limit Ratio vs Current limit Value With Percent Error

Using this figure, the error can be estimated for any current limit value desired, and the associated KCL value can determine the RILIM resistor appropriate. This graph does not take into account RILIM resistor tolerances, only the error associated with the current limit regulation.