SLVSGK4A November   2021  – June 2022 TPS22953-Q1 , TPS22954-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3.     Recommended Operating Conditions
    4. 7.3  Thermal Information
    5. 7.4  Electrical Characteristics
    6. 7.5  Electrical Characteristics – VBIAS = 5 V
    7. 7.6  Electrical Characteristics – VBIAS = 3.3 V
    8. 7.7  Electrical Characteristics – VBIAS = 2.5 V
    9. 7.8  Switching Characteristics – CT = 1000 pF
    10. 7.9  Switching Characteristics – CT = 0 pF
    11. 7.10 Typical DC Characteristics
    12. 7.11 Typical Switching Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  On and Off Control (EN Pin)
      2. 9.3.2  Voltage Monitoring (SNS Pin)
      3. 9.3.3  Power Good (PG Pin)
      4. 9.3.4  Supervisor Fault Detection and Automatic Restart
      5. 9.3.5  Manual Restart
      6. 9.3.6  Thermal Shutdown
      7. 9.3.7  Reverse Current Blocking (TPS22953-Q1 Only)
      8. 9.3.8  Quick Output Discharge (QOD) (TPS22954-Q1 Only)
      9. 9.3.9  VIN and VBIAS Voltage Range
      10. 9.3.10 Adjustable Rise Time (CT Pin)
      11. 9.3.11 Power Sequencing
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Input to Output Voltage Drop
      2. 10.1.2 Thermal Considerations
      3. 10.1.3 Automatic Power Sequencing
      4. 10.1.4 Monitoring a Downstream Voltage
      5. 10.1.5 Monitoring the Input Voltage
      6. 10.1.6 Break-Before-Make Power MUX (TPS22953-Q1 Only)
      7. 10.1.7 Make-Before-Break Power MUX (TPS22953-Q1 Only)
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Inrush Current
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Support Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10.1.7 Make-Before-Break Power MUX (TPS22953-Q1 Only)

The reverse current blocking feature of the TPS22953-Q1 makes it suitable for power multiplexing (MUXing) between two power supplies with different voltages. The SNS and PG pin can be configured to implement make-before-break logic. The circuit in Figure 10-5 shows how the detection of Load Switch 1 turning on can be used to disable the load switch for power supply 2. By tying SNS to the Load, the PG is pulled up when the output voltage starts to rise. This event disables an active low load switch such as the TPS22910A.

GUID-20211110-SS0I-CP0W-LDZJ-W7MDDTKKTNPN-low.pngFigure 10-5 Make-Before-Break Power MUX Schematic

The make-before-break logic ensures that power supply 2 is not disconnected until power supply 1 is connected. Unlike break-before-make logic, this approach is ideal for preventing voltage dip on the output when switching between supplies. However, in most cases, this approach also results in temporary reverse current flow.

The TPS22910A is well suited for this application because it can detect and block reverse current even before it is disabled by the TPS22953-Q1 PG signal. Also, the active low enable of the TPS22910A eliminates the need for an inverter as shown in the previous example.

To ensure correct logic, the SNS pin must be configured to toggle PG when the load voltage is between the two supply voltages (3.6 V to 4.5 V). The SNS resistor values in Figure 10-5 are assuming a tolerance of ±1% or better.

Table 10-2 summarizes the logic of the PG Signal for Figure 10-5.

Table 10-2 Make-Before-Break PG Signal
PG SignalIndication
HPower supply 1 present. System powered from power supply 1.
LPower supply 1 not present. System powered from power supply 2.