SLVS885I October   2008  – December 2017 TPS23754 , TPS23754-1 , TPS23756


  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      High-Efficiency Converter Using TPS23754
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Electrical Characteristics: PoE and Control
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  APD
      2. 7.3.2  BLNK
      3. 7.3.3  CLS
      4. 7.3.4  Current Sense (CS)
      5. 7.3.5  Control (CTL)
      6. 7.3.6  Detection and Enable (DEN)
      7. 7.3.7  DT
      8. 7.3.8  Frequency and Synchronization (FRS)
      9. 7.3.9  GATE
      10. 7.3.10 GAT2
      11. 7.3.11 PPD
      12. 7.3.12 RTN, ARTN, COM
      13. 7.3.13 T2P
      14. 7.3.14 VB
      15. 7.3.15 VC
      16. 7.3.16 VDD
      17. 7.3.17 VDD1
      18. 7.3.18 VSS
      19. 7.3.19 PowerPAD
    4. 7.4 Device Functional Modes
      1. 7.4.1 PoE Overview
        1.  Threshold Voltages
        2.  PoE Start-Up Sequence
        3.  Detection
        4.  Hardware Classification
        5.  Inrush and Start-Up
        6.  Maintain Power Signature
        7.  Start-Up and Converter Operation
        8.  PD Hotswap Operation
        9.  Converter Controller Features
        10. Bootstrap Topology
        11. Current Slope Compensation and Current Limit
        12. Blanking – RBLNK
        13. Dead Time
        14. FRS and Synchronization
        15. T2P, Start-Up, and Power Management
        16. Thermal Shutdown
        17. Adapter ORing
        18. PPD ORing Features
        19. Using DEN to Disable PoE
        20. ORing Challenges
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1.  Input Bridges and Schottky Diodes
        2.  Protection, D1
        3.  Capacitor, C1
        4.  Detection Resistor, RDEN
        5.  Classification Resistor, RCLS
        6.  Dead Time Resistor, RDT
        7.  Switching Transformer Considerations and RVC
        8.  Special Switching MOSFET Considerations
        9.  Thermal Considerations and OTSD
        10. APD Pin Divider Network, RAPD1, RAPD2
        11. PPD Pin Divider Network, RPPD1, RPPD2
        12. Setting Frequency (RFRS) and Synchronization
        13. Current Slope Compensation
        14. Blanking Period, RBLNK
        15. Estimating Bias Supply Requirements and CVC
        16. T2P Pin Interface
        17. Advanced ORing Techniques
        18. Soft Start
        19. Frequency Dithering for Conducted Emissions Control
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 ESD
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PWP|20
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Start-Up and Converter Operation

The internal PoE undervoltage lockout (UVLO) circuit holds the hotswap switch off before the PSE provides full voltage to the PD. This prevents the converter circuits from loading the PoE input during detection and classification. The converter circuits discharge CIN, CVC, and CVB while the PD is unpowered. Thus VVDD-VRTN will be a small voltage just after full voltage is applied to the PD, as seen in Figure 22. The PSE drives the PI voltage to the operating range once it has decided to power up the PD. When VVDD rises above the UVLO turnon threshold (VUVLO-R, about 35 V) with RTN high, the TPS23754 device enables the hotswap MOSFET with an approximately 140-mA (inrush) current limit as seen in Figure 24. Converter switching is disabled while CIN charges and VRTN falls from VVDD to nearly VVSS, however the converter start-up circuit is allowed to charge CVC (the bootstrap start-up capacitor). Additional loading applied between VVDD and VRTN during the inrush state may prevent successful PD and subsequent converter start-up. Converter switching is allowed if the PD is not in inrush, OTSD is not active, and the VC UVLO permits it. Once the inrush current falls about 10% less than the inrush current limit, the PD current limit switches to the operational level (about 970 mA). Continuing the start-up sequence shown in Figure 24, VVC continues to rise until the start-up threshold (VCUV, about 15 V or about 9 V) is exceeded, turning the start-up source off and enabling switching. The VB regulator is always active, powering the internal converter circuits as VVC rises. There is a slight delay between the removal of charge current and the start of switching as the soft-start ramp sweeps above the VZDC threshold. VVC falls as it powers both the internal circuits and the switching MOSFET gates. If the converter control bias output rises to support VVC before it falls to VCUV – VCUVH (about 8.5 V or about 5.5 V), a successful start-up occurs. T2P in Figure 22 (Figure 27, VT2P-OUT) becomes active within tT2P from the start of switching, indicating that a type 2 PSE or an adapter is plugged in.

TPS23754 TPS23754-1 TPS23756 pwr_up2_lvs885.gifFigure 24. Power Up and Start

If VVDD- VVSS drops below the lower PoE UVLO (VUVLO-R - VUVLO-H, about 30.5 V), the hotswap MOSFET is turned off, but the converter will still run. The converter will stop if VVC falls below the converter UVLO (VCUV – VCUVH, about 8.5 V or about 5.5 V), the hotswap is in inrush current limit, 0% duty cycle is demanded by VCTL (VCTL < VZDC, about 1.5 V), or the converter is in thermal shutdown.