SLVSDW2B December 2018 – November 2020 TPS23755
PRODUCTION DATA
The TPS23755 device DC-DC controller implements a typical current-mode control as shown in Functional Block Diagram. Features include oscillator, overcurrent and PWM comparators, current-sense blanker, soft start, gate driver and switching power FET. In addition, an internal current-compensation ramp generator, frequency synchronization logic, built-in frequency dithering functionality, thermal shutdown, and start-up current source with control are provided.
The TPS23755 is optimized for isolated converters, and it includes an internal error amplifier. The voltage feedback is from the bias winding. The COMP output of the error amplifier is directly fed to a 2:1 internal resistor divider and an offset of VZDC/2 (approximately 0.75 V) which defines a current-demand control for the pulse width modulator (PWM). A VCOMP below VZDC stops converter switching, while voltages above (VZDC + 2 × (VCSMAX + VSLOPE)) does not increase the requested peak current in the switching MOSFET.
The internal start-up current source and control logic implement a bootstrap-type startup. The startup current source charges CCC from VDD and maintain its voltage when the converter is disabled or during the soft-start period, while operational power must come from a converter (bias winding) output.
The bootstrap source provides reliable start-up from widely varying input voltages, and eliminates the continual power loss of external resistors.
The peak current limit does not have duty cycle dependency unless RS is used as shown in Figure 7-2 to increase slope compensation. This makes it easier to design the current limit to a fixed value.
The DC-DC controller has an OTSD that can be triggered by heat sources including the power switching FET and GATE driver. The controller OTSD turns off the switching FET and resets the soft-start generator.