SLUSBX9I March   2014  – July 2019 TPS23861

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Simplified Schematic
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
      1. 7.1.1 Detailed Pin Description
      2. 7.1.2 I2C Detailed Pin Description
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Detection Resistance Measurement
      2. 7.3.2  Physical Layer Classification
      3. 7.3.3  Class and Detect Fields
      4. 7.3.4  Register State Following a Fault
      5. 7.3.5  Disconnect
      6. 7.3.6  Disconnect Threshold
      7. 7.3.7  Fast Shutdown Mode
      8. 7.3.8  Legacy Device Detection
      9. 7.3.9  VPWR Undervoltage and UVLO Events
      10. 7.3.10 Timer-Deferrable Interrupt Support
      11. 7.3.11 A/D Converter and I2C Interface
      12. 7.3.12 Independent Operation when the AUTO Bit is Set
      13. 7.3.13 I2C Slave Address and AUTO Bit Programming
    4. 7.4 Device Functional Modes
      1. 7.4.1 Off
      2. 7.4.2 Manual
      3. 7.4.3 Semi-Auto
      4. 7.4.4 Auto
      5. 7.4.5 Push-Button Power On Response
      6. 7.4.6 TSTART Indicators of Detect and Class Failures
      7. 7.4.7 Device Power On Initialization
    5. 7.5 Register Map – I2C-Addressable
      1. 7.5.1  Interrupt Register
      2. 7.5.2  Interrupt Enable Register
      3. 7.5.3  Power Event Register
      4. 7.5.4  Detection Event Register
      5. 7.5.5  Fault Event Register
      6. 7.5.6  Start/ILIM Event Register
      7. 7.5.7  Supply Event Register
      8. 7.5.8  Port n Status Register
        1. 7.5.8.1 Port 1 Status Register
        2. 7.5.8.2 Port 2 Status Register
        3. 7.5.8.3 Port 3 Status Register
        4. 7.5.8.4 Port 4 Status Register
      9. 7.5.9  Power Status Register
      10. 7.5.10 I2C Slave Address Register
      11. 7.5.11 Operating Mode Register
      12. 7.5.12 Disconnect Enable Register
      13. 7.5.13 Detect/Class Enable Register
      14. 7.5.14 Port Power Priority Register
      15. 7.5.15 Timing Configuration Register
      16. 7.5.16 General Mask 1 Register
      17. 7.5.17 Detect/Class Restart Register
      18. 7.5.18 Power Enable Register
      19. 7.5.19 Reset Register
      20. 7.5.20 Legacy Detect Mode Register
      21. 7.5.21 Two-Event Classification Register
      22. 7.5.22 Interrupt Timer Register
      23. 7.5.23 Disconnect Threshold Register
        1. 7.5.23.1 Bits Description
      24. 7.5.24 ICUTnm CONFIG Register
        1. 7.5.24.1 ICUT21 CONFIG Register
        2. 7.5.24.2 ICUT43 CONFIG Register
        3. 7.5.24.3 Bits Description
      25. 7.5.25 Temperature Register
      26. 7.5.26 Input Voltage Register
      27. 7.5.27 Port n Current Register
        1. 7.5.27.1 Port 1 Current Register
        2. 7.5.27.2 Port 2 Current Register
        3. 7.5.27.3 Port 3 Current Register
        4. 7.5.27.4 Port 4 Current Register
      28. 7.5.28 Port n Voltage Register
        1. 7.5.28.1 Port 1 Voltage Register
        2. 7.5.28.2 Port 2 Voltage Register
        3. 7.5.28.3 Port 3 Voltage Register
        4. 7.5.28.4 Port 4 Voltage Register
      29. 7.5.29 PoE Plus Register
      30. 7.5.30 Firmware Revision Register
      31. 7.5.31 I2C Watchdog Register
      32. 7.5.32 Device ID Register
      33. 7.5.33 Cool Down/Gate Drive Register
      34. 7.5.34 Port n Detect Resistance Register
        1. 7.5.34.1 Port 1 Detect Resistance Register
          1. 7.5.34.1.1 Port 2 Detect Resistance Register
          2. 7.5.34.1.2 Port 3 Detect Resistance Register
          3. 7.5.34.1.3 Port 4 Detect Resistance Register
      35. 7.5.35 Port n Detect Voltage Difference Register
        1. 7.5.35.1 Port 1 Detect Voltage Difference Register
        2. 7.5.35.2 Port 2 Detect Voltage Difference Register
        3. 7.5.35.3 Port 3 Detect Voltage Difference Register
        4. 7.5.35.4 Port 4 Detect Voltage Difference Register
      36. 7.5.36 Reserved Registers
  8. Application and Implementation
    1. 8.1 Introduction to PoE
    2. 8.2 Application Information
      1. 8.2.1 Kelvin Current Sensing Resistor
      2. 8.2.2 Connections on Unused Ports
    3. 8.3 Typical Application
      1. 8.3.1 Two Port, Auto Mode Application with External Port Reset
        1. 8.3.1.1 Design Requirements
      2. 8.3.2 Four Port, Auto Mode Application
        1. 8.3.2.1 Design Requirements
      3. 8.3.3 Eight Port, Semi-Auto Mode Application Using MSP430 Micro-Controller
        1. 8.3.3.1 Design Requirements
      4. 8.3.4 Detailed Design Procedure
        1. 8.3.4.1 Power Pin Bypass Capacitors
        2. 8.3.4.2 Per Port Components
        3. 8.3.4.3 System Level Components (not shown in the schematic diagrams)
      5. 8.3.5 Application Curves
    4. 8.4 System Examples
      1. 8.4.1 Overcurrent and Overload Protection
      2. 8.4.2 Inrush Protection
      3. 8.4.3 ICUT Current Limit
      4. 8.4.4 Foldback Protection (ILIM)
      5. 8.4.5 Kelvin Current Sensing Resistor
  9. Power Supply Recommendations
    1. 9.1 VDD
    2. 9.2 VPWR
    3. 9.3 VPWR-RESET Sequencing
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Port Current Kelvin Sensing
    2. 10.2 Layout Example
      1. 10.2.1 Component Placement and Routing Guidelines
        1. 10.2.1.1 Power Pin Bypass Capacitors
        2. 10.2.1.2 Per-Port Components
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

I2C Slave Address and AUTO Bit Programming

NOTE

When using the I2C interface the host software should wait 22 ms minimum after a reset to ensure valid I2C transactions.

NOTE

Please note EEPROM endurance of 25 write cycles. Writing to the EEPROM more than this may result in erratic behavior.

The TPS23861 includes a means to program in EEPROM the following two fields:

  • A seven bit I2C slave address for operation with a host processor.
  • AUTO bit which allows the TPS23861 to operate independently without a host processor.

The benefits this approach include:

  • Up to 125 similar devices become addressable.
  • Provides a high level of flexibility.
    • Helps to resolve conflicts with other peripherals on same I2C bus.
    • The I2C address can be programmed at production subassembly module level or motherboard level.
    • Allows a simple approach to field-installed upgrades or expansions to PSE systems.
  • No physical address line required, no bank selection required.
  • Smaller package. No address line pins and no AUTO pin.

NOTE

For compatibility with legacy systems, the module A3 bank addressing is provided by use of the A3 input pin.

As shown in Figure 41, the initial I2C address programming access is established by a local daisy chain chip select connection between multiple TPS23861 devices. The AIN pin plays the role of a “moving chip select” during address programming.

NOTE

Global write command including an unlock code (AAh) is required in order to write to the I2C slave address register.

TPS23861 I2C_Slave_lusbw2.gifFigure 41. I2C Slave Address and AUTO Bit Programming Circuit

The sequence during address programming is as follows:

  • Global write command including an unlock code (AAh) and a temporary common slave address (any address other than 30h) is sent to all I2C devices through the broadcast address, 30h.
  • All TPS23861 devices respond to the broadcast address 30h regardless of the state of the A3 pin. When the three-byte sequence is correctly decoded,
    1. Each TPS23861 has a new I2C address determined by the programmed temporary slave address with bit 3 equal to the state of the A3 pin.
    2. All TPS23861 devices force low the AOUT output.
    For example, if a temporary common slave address of 20h is written to one device with A3 low and one with A3 high, the device with A3 low will respond to I2C address 20h and the device with A3 high responds to I2C address 28h.
  • The first TPS23861 device being selected is the only one having its AIN pin at logic high level (U1 in Figure 41).
  • Using the temporary slave address, write the new 7-bit device address in the I2C slave address register. See data format below.
  • NOTE

    The SLA3 slave address bit follows the logic level of A3 input pin, as detailed for I2C Slave Address register.

    BITS D7 D6 D5 D4 D3 D2 D1 D0
    BIT NAME AUTO 7-bit I2C Address
  • The first slave accepts the new address, then forces its AOUT output pin to high level and automatically locks the access to its slave address register. It also stores permanently its new slave address into EEPROM.
  • The same procedure is repeated for the next slave device, which has just detected that its AIN input has become high.
  • This is repeated until all slaves have been reprogrammed.
  • The host can then interrogate each slave, one by one, in order to validate their new address.
  • NOTE

    During the address programming procedure if the slave has not received its new address within a timeout period (around 100 ms), it goes back to the initial slave address (before the address programming sequence was initiated); it locks its address register and releases its AOUT output.

  • Bit 7 of the 8-bit transfer (AUTO) defines if the controller operates independently (no host processor) as an automatic PSE. The state of this bit is monitored only immediately following a power-on reset, writing a 1 to the RESAL bit of the RESET register, or after the RESET input has been activated. The impact of that bit state on registers after reset is reflected in the Table 10 (Reset State column) and is referred to as “A”.
  • NOTE

    After programming a new I2C slave address to register 0×11, a 100 ms delay is recommended before trying to perform a read check.

    NOTE

    When using I2C scan for device discovery, it is recommended to add at least a 100 ms delay between writing commands to address 0x30 (Broadcast address) and 0x31. This prevents receiving unnecessary extra ACK. Skipping writing command to address 0x30 can also avoid the extra ACK.

TPS23861 fig42a_lusbx9.gifFigure 42. I2C/SMBus Interface Slave Address Programming Protocol
TPS23861 Interrupt_Logic_Func_Diag_SLUSBX9.gifFigure 43. Interrupt Logic Functional Diagram