SLUSBX9I March   2014  – July 2019 TPS23861

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
      1. 7.1.1 Detailed Pin Description
      2. 7.1.2 I2C Detailed Pin Description
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Detection Resistance Measurement
      2. 7.3.2  Physical Layer Classification
      3. 7.3.3  Class and Detect Fields
      4. 7.3.4  Register State Following a Fault
      5. 7.3.5  Disconnect
      6. 7.3.6  Disconnect Threshold
      7. 7.3.7  Fast Shutdown Mode
      8. 7.3.8  Legacy Device Detection
      9. 7.3.9  VPWR Undervoltage and UVLO Events
      10. 7.3.10 Timer-Deferrable Interrupt Support
      11. 7.3.11 A/D Converter and I2C Interface
      12. 7.3.12 Independent Operation when the AUTO Bit is Set
      13. 7.3.13 I2C Slave Address and AUTO Bit Programming
    4. 7.4 Device Functional Modes
      1. 7.4.1 Off
      2. 7.4.2 Manual
      3. 7.4.3 Semi-Auto
      4. 7.4.4 Auto
      5. 7.4.5 Push-Button Power On Response
      6. 7.4.6 TSTART Indicators of Detect and Class Failures
      7. 7.4.7 Device Power On Initialization
    5. 7.5 Register Map – I2C-Addressable
      1. 7.5.1  Interrupt Register
      2. 7.5.2  Interrupt Enable Register
      3. 7.5.3  Power Event Register
      4. 7.5.4  Detection Event Register
      5. 7.5.5  Fault Event Register
      6. 7.5.6  Start/ILIM Event Register
      7. 7.5.7  Supply Event Register
      8. 7.5.8  Port n Status Register
        1. 7.5.8.1 Port 1 Status Register
        2. 7.5.8.2 Port 2 Status Register
        3. 7.5.8.3 Port 3 Status Register
        4. 7.5.8.4 Port 4 Status Register
      9. 7.5.9  Power Status Register
      10. 7.5.10 I2C Slave Address Register
      11. 7.5.11 Operating Mode Register
      12. 7.5.12 Disconnect Enable Register
      13. 7.5.13 Detect/Class Enable Register
      14. 7.5.14 Port Power Priority Register
      15. 7.5.15 Timing Configuration Register
      16. 7.5.16 General Mask 1 Register
      17. 7.5.17 Detect/Class Restart Register
      18. 7.5.18 Power Enable Register
      19. 7.5.19 Reset Register
      20. 7.5.20 Legacy Detect Mode Register
      21. 7.5.21 Two-Event Classification Register
      22. 7.5.22 Interrupt Timer Register
      23. 7.5.23 Disconnect Threshold Register
        1. 7.5.23.1 Bits Description
      24. 7.5.24 ICUTnm CONFIG Register
        1. 7.5.24.1 ICUT21 CONFIG Register
        2. 7.5.24.2 ICUT43 CONFIG Register
        3. 7.5.24.3 Bits Description
      25. 7.5.25 Temperature Register
      26. 7.5.26 Input Voltage Register
      27. 7.5.27 Port n Current Register
        1. 7.5.27.1 Port 1 Current Register
        2. 7.5.27.2 Port 2 Current Register
        3. 7.5.27.3 Port 3 Current Register
        4. 7.5.27.4 Port 4 Current Register
      28. 7.5.28 Port n Voltage Register
        1. 7.5.28.1 Port 1 Voltage Register
        2. 7.5.28.2 Port 2 Voltage Register
        3. 7.5.28.3 Port 3 Voltage Register
        4. 7.5.28.4 Port 4 Voltage Register
      29. 7.5.29 PoE Plus Register
      30. 7.5.30 Firmware Revision Register
      31. 7.5.31 I2C Watchdog Register
      32. 7.5.32 Device ID Register
      33. 7.5.33 Cool Down/Gate Drive Register
      34. 7.5.34 Port n Detect Resistance Register
        1. 7.5.34.1 Port 1 Detect Resistance Register
          1. 7.5.34.1.1 Port 2 Detect Resistance Register
          2. 7.5.34.1.2 Port 3 Detect Resistance Register
          3. 7.5.34.1.3 Port 4 Detect Resistance Register
      35. 7.5.35 Port n Detect Voltage Difference Register
        1. 7.5.35.1 Port 1 Detect Voltage Difference Register
        2. 7.5.35.2 Port 2 Detect Voltage Difference Register
        3. 7.5.35.3 Port 3 Detect Voltage Difference Register
        4. 7.5.35.4 Port 4 Detect Voltage Difference Register
      36. 7.5.36 Reserved Registers
  8. 8 Application and Implementation
    1. 8.1 Introduction to PoE
    2. 8.2 Application Information
      1. 8.2.1 Kelvin Current Sensing Resistor
      2. 8.2.2 Connections on Unused Ports
    3. 8.3 Typical Application
      1. 8.3.1 Two Port, Auto Mode Application with External Port Reset
        1. 8.3.1.1 Design Requirements
      2. 8.3.2 Four Port, Auto Mode Application
        1. 8.3.2.1 Design Requirements
      3. 8.3.3 Eight Port, Semi-Auto Mode Application Using MSP430 Micro-Controller
        1. 8.3.3.1 Design Requirements
      4. 8.3.4 Detailed Design Procedure
        1. 8.3.4.1 Power Pin Bypass Capacitors
        2. 8.3.4.2 Per Port Components
        3. 8.3.4.3 System Level Components (not shown in the schematic diagrams)
      5. 8.3.5 Application Curves
    4. 8.4 System Examples
      1. 8.4.1 Overcurrent and Overload Protection
      2. 8.4.2 Inrush Protection
      3. 8.4.3 ICUT Current Limit
      4. 8.4.4 Foldback Protection (ILIM)
      5. 8.4.5 Kelvin Current Sensing Resistor
  9. 9 Power Supply Recommendations
    1. 9.1 VDD
    2. 9.2 VPWR
    3. 9.3 VPWR-RESET Sequencing
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Port Current Kelvin Sensing
    2. 10.2 Layout Example
      1. 10.2.1 Component Placement and Routing Guidelines
        1. 10.2.1.1 Power Pin Bypass Capacitors
        2. 10.2.1.2 Per-Port Components
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5.35.4 Port 4 Detect Voltage Difference Register

Command = 6Eh with 2 Data Byte (LSByte first, MSByte second), Read

LSB: 6Eh

BITS D7 D6 D5 D4 D3 D2 D1 D0
BIT NAME Port 4 Voltage Difference [7:0]
RESET or POR VALUE 0 0 0 0 0 0 0 0

MSB: 6Fh

BITS D7 D6 D5 D4 D3 D2 D1 D0
BIT NAME VDS4[3:0] Port 4 Voltage Difference [11:8]
RESET or POR VALUE 0 0 0 0 0 0 0 0

This register is used to determine the presence of a legacy PD by measuring the PD input capacitance on the PI. A charge is injected into the PI, and the resulting Δv is reported. The Δv value shown is useable only if VDSn[3:0] = 0001.

The I2C data transmission is a 2-byte transfer.

Bit Descriptions

Port n Voltage Difference[11:0]: 12-bit data conversion result of the difference in voltage on the port as a result of a fixed charge injected into the port. The equation defining the resistance measured is:

Equation 7. TPS23861 qu6_lusbw2.gif

where

  • C = Port capacitance, F
  • k = 81 x 10-6 coulomb
  • N = 12-bit value in Port n Detect Voltage Difference Register
  • VSTEP = LSB Value

NOTE

The expression for port capacitance ignores the effect of any conductance in parallel with the capacitance being measured. The effect of parallel conductance is to give a higher value than the actual value of any capacitance present.

USEABLE CAPACITANCE RANGE VOLTAGE DIFFERENCE LSB VALUE
10 to 100 µF 4.884 mV

VDSn[3:0]: Most recent detect voltage difference result status on Port n. If “0001” state, the 12-bit Δv value is useable.

This measurement is made on a port if legacy detect is enabled using the Legacy Detect Mode Register.

VDSn is set to the Power-On Reset State (0000b) when legacy detection is enabled until a Δv measurement is made.

The detection result is maintained in the register in any operating mode following the measurement.

The selection is as following:

VDSn[3:0] VOLTAGE-DIFFERENCE MEASUREMENT STATUS
0000 Power-on reset
0001 Valid measurement
0010 Unable to discharge PD input capacitance to 2.4 V before timeout
0011 Unable to achieve 0.4V to take first measurement before timeout
0100 First measurement exceeds VDet-clamp (min)
0101 Second measurement exceeds VDet-clamp (min)
0110 ΔV < 0.5 V (insufficient signal)