SLUSBX9I March   2014  – July 2019 TPS23861

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
      1. 7.1.1 Detailed Pin Description
      2. 7.1.2 I2C Detailed Pin Description
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Detection Resistance Measurement
      2. 7.3.2  Physical Layer Classification
      3. 7.3.3  Class and Detect Fields
      4. 7.3.4  Register State Following a Fault
      5. 7.3.5  Disconnect
      6. 7.3.6  Disconnect Threshold
      7. 7.3.7  Fast Shutdown Mode
      8. 7.3.8  Legacy Device Detection
      9. 7.3.9  VPWR Undervoltage and UVLO Events
      10. 7.3.10 Timer-Deferrable Interrupt Support
      11. 7.3.11 A/D Converter and I2C Interface
      12. 7.3.12 Independent Operation when the AUTO Bit is Set
      13. 7.3.13 I2C Slave Address and AUTO Bit Programming
    4. 7.4 Device Functional Modes
      1. 7.4.1 Off
      2. 7.4.2 Manual
      3. 7.4.3 Semi-Auto
      4. 7.4.4 Auto
      5. 7.4.5 Push-Button Power On Response
      6. 7.4.6 TSTART Indicators of Detect and Class Failures
      7. 7.4.7 Device Power On Initialization
    5. 7.5 Register Map – I2C-Addressable
      1. 7.5.1  Interrupt Register
      2. 7.5.2  Interrupt Enable Register
      3. 7.5.3  Power Event Register
      4. 7.5.4  Detection Event Register
      5. 7.5.5  Fault Event Register
      6. 7.5.6  Start/ILIM Event Register
      7. 7.5.7  Supply Event Register
      8. 7.5.8  Port n Status Register
        1. 7.5.8.1 Port 1 Status Register
        2. 7.5.8.2 Port 2 Status Register
        3. 7.5.8.3 Port 3 Status Register
        4. 7.5.8.4 Port 4 Status Register
      9. 7.5.9  Power Status Register
      10. 7.5.10 I2C Slave Address Register
      11. 7.5.11 Operating Mode Register
      12. 7.5.12 Disconnect Enable Register
      13. 7.5.13 Detect/Class Enable Register
      14. 7.5.14 Port Power Priority Register
      15. 7.5.15 Timing Configuration Register
      16. 7.5.16 General Mask 1 Register
      17. 7.5.17 Detect/Class Restart Register
      18. 7.5.18 Power Enable Register
      19. 7.5.19 Reset Register
      20. 7.5.20 Legacy Detect Mode Register
      21. 7.5.21 Two-Event Classification Register
      22. 7.5.22 Interrupt Timer Register
      23. 7.5.23 Disconnect Threshold Register
        1. 7.5.23.1 Bits Description
      24. 7.5.24 ICUTnm CONFIG Register
        1. 7.5.24.1 ICUT21 CONFIG Register
        2. 7.5.24.2 ICUT43 CONFIG Register
        3. 7.5.24.3 Bits Description
      25. 7.5.25 Temperature Register
      26. 7.5.26 Input Voltage Register
      27. 7.5.27 Port n Current Register
        1. 7.5.27.1 Port 1 Current Register
        2. 7.5.27.2 Port 2 Current Register
        3. 7.5.27.3 Port 3 Current Register
        4. 7.5.27.4 Port 4 Current Register
      28. 7.5.28 Port n Voltage Register
        1. 7.5.28.1 Port 1 Voltage Register
        2. 7.5.28.2 Port 2 Voltage Register
        3. 7.5.28.3 Port 3 Voltage Register
        4. 7.5.28.4 Port 4 Voltage Register
      29. 7.5.29 PoE Plus Register
      30. 7.5.30 Firmware Revision Register
      31. 7.5.31 I2C Watchdog Register
      32. 7.5.32 Device ID Register
      33. 7.5.33 Cool Down/Gate Drive Register
      34. 7.5.34 Port n Detect Resistance Register
        1. 7.5.34.1 Port 1 Detect Resistance Register
          1. 7.5.34.1.1 Port 2 Detect Resistance Register
          2. 7.5.34.1.2 Port 3 Detect Resistance Register
          3. 7.5.34.1.3 Port 4 Detect Resistance Register
      35. 7.5.35 Port n Detect Voltage Difference Register
        1. 7.5.35.1 Port 1 Detect Voltage Difference Register
        2. 7.5.35.2 Port 2 Detect Voltage Difference Register
        3. 7.5.35.3 Port 3 Detect Voltage Difference Register
        4. 7.5.35.4 Port 4 Detect Voltage Difference Register
      36. 7.5.36 Reserved Registers
  8. 8 Application and Implementation
    1. 8.1 Introduction to PoE
    2. 8.2 Application Information
      1. 8.2.1 Kelvin Current Sensing Resistor
      2. 8.2.2 Connections on Unused Ports
    3. 8.3 Typical Application
      1. 8.3.1 Two Port, Auto Mode Application with External Port Reset
        1. 8.3.1.1 Design Requirements
      2. 8.3.2 Four Port, Auto Mode Application
        1. 8.3.2.1 Design Requirements
      3. 8.3.3 Eight Port, Semi-Auto Mode Application Using MSP430 Micro-Controller
        1. 8.3.3.1 Design Requirements
      4. 8.3.4 Detailed Design Procedure
        1. 8.3.4.1 Power Pin Bypass Capacitors
        2. 8.3.4.2 Per Port Components
        3. 8.3.4.3 System Level Components (not shown in the schematic diagrams)
      5. 8.3.5 Application Curves
    4. 8.4 System Examples
      1. 8.4.1 Overcurrent and Overload Protection
      2. 8.4.2 Inrush Protection
      3. 8.4.3 ICUT Current Limit
      4. 8.4.4 Foldback Protection (ILIM)
      5. 8.4.5 Kelvin Current Sensing Resistor
  9. 9 Power Supply Recommendations
    1. 9.1 VDD
    2. 9.2 VPWR
    3. 9.3 VPWR-RESET Sequencing
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Port Current Kelvin Sensing
    2. 10.2 Layout Example
      1. 10.2.1 Component Placement and Routing Guidelines
        1. 10.2.1.1 Power Pin Bypass Capacitors
        2. 10.2.1.2 Per-Port Components
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5.15 Timing Configuration Register

Command = 16h with 1 Data Byte, R/W

BITS D7 D6 D5 D4 D3 D2 D1 D0
BIT NAME TLIM TSTART TICUT TDIS
RESET or POR VALUE 0 0 0 0 0 0 0 0

These bits define the timing configuration for all four ports.

NOTE

The PGn and PEn bits in the Power Status Register are cleared when there is a Start, ICUT or ILIM condition.

Bit Descriptions

TLIM[1:0]: ILIM fault timing, which is the foldback current limit time duration before port turn off. This timer is loaded with its maximum count corresponding to tLIM after expiration of the tSTART period; the timer counts down when the port is limiting its output current to ILIM. If the ILIM timer counts down to zero, the port is powered off. After the port is powered off the cool-down period commences. The cool-down period is selected by the CLDN field in the Cool Down/Gate Drive register. During the cool-down period the port will not engage in detection, classification, or powered-up operation. When the port is powered up and while the port current is below ILIM, the same counter increments at a rate 1/16th of the count-down rate (independent of the setting in the CLDN field). The counter does not increment past the maximum count corresponding to the programmed TLIM value.

NOTE

At the end of the cool-down period, when in Semi-Auto or Auto Mode, a detection cycle is automatically restarted if the detect enable bit is set.

NOTE

If ILIM and ICUT are set to same value, it is a race condition between ILIM and ICUT in TPS23861 and it depends on the firmware as to the winner.

When a POEPn bit in the PoE Plus Register is cleared, the tLIM used for the associated port is always the nominal value (~60 ms). If the POEPn bit is set, then tLIM for associated port is programmable with the following selection:

TLIM[1:0] NOMINAL tLIM (ms) WHEN PoEPn BIT IS SET
00 60
01 30
10 15
11 10

TSTART[1:0]: This 2-bit field sets the length of the tSTART period, which is the maximum allowed overcurrent time during inrush. If at the end of the tSTART period the current is still limited to IINRUSH , the port is powered off. This is followed by a cool-down period, set with the CLDN field in the Cool Down/Gate Drive Register, during which the port cannot be turned on if in Semi-Auto or Auto Mode.

NOTE

At the end of cool-down cycle, when in Semi-Auto or Auto Mode, a detection cycle is automatically restarted if the class and detect enable bits are set.

The selection is as following:

TSTART [1:0] NOMINAL tSTART (ms)
00 60
01 30
10 120
11 Reserved

TICUT[1:0]: ICUT fault timing, which is the overcurrent time duration before port turn off (tOVLD).

This timer is loaded with its maximum count corresponding to tOVLD after expiration of the tSTART period; the timer counts down when the port current exceeds ICUT. If the ICUT timer counts down to zero, the port is powered off. After the port is powered off the cool-down period commences. The cool-down period is set with the CLDN field in the Cool Down/Gate Drive Register. During the cool-down period the port will not engage in detection, classification, or powered-up operation. When the port is powered up and while the port current is below ICUT, the same counter increments at a rate 1/16th of the count-down rate (independent of the setting in the CLDN field). The counter does not increment past the maximum count corresponding to the programmed TICUT value.

NOTE

At the end of cool-down cycle, when in Semi-Auto or Auto Mode, a detection cycle is automatically restarted if the detect enable bit is set.

NOTE

If ILIM and ICUT are set to same value, it is a race condition between ILIM and ICUT in TPS23861 and it depends on the firmware as to the winner.

The selection is as following:

TICUT[1:0] NOMINAL tOVLD (ms)
00 60
01 30
10 120
11 240

TDIS[1:0]: Disconnect delay, which is the time to turn off a port once there is a disconnect condition.

After port power on and the completion of the tSTART period the TDIS counter is started when the port current drops below the disconnect threshold established in the DCTHn fields, and the counter is reset each time the current goes continuously higher than the disconnect threshold for 13% of tMPDO. The counter does not decrement below zero. The selection is as following:

TDIS[1:0] NOMINAL tMPDO (ms)
0 0 360
0 1 90
1 0 180
1 1 720