SLVSF02D March 2019 – May 2020 TPS23881
COMMAND = 40h with1 Data Byte Read/Write
|R/W-0||R/W-0||R/W-0||R/W-0||R/W -0||R/W -0||R/W -0||R/W -0|
|LEGEND: R/W = Read/Write; R = Read only; -n = value after reset|
|7–4||2xFB4- 2xFB1||R/W||0||When set, this activates the 2x Foldback mode for a channel which increases its ILIM and ISHORT levels normal settings, as shown in Figure 40. Note that the fault timer starts when the ILIM threshold is exceeded.|
|1)||At turn on, the inrush current profile is unaffected by these bits, as shown in Figure 39.|
|2)||When a 2xFBn bit is deasserted, the tLIM setting used for the associated channel is always the nominal value (approximately 60 ms). If 2xFBn bit is asserted, then tLIM for associated channel is programmable as defined in the Timing Configuration register (0x16).|
|3)||If the assigned class for a channel is class 4 or above, the 2xFB bit will be automatically set during turn on.
For a single signature 4-pair powered PD both bits will be set
For a dual signature 4-pair powered PD each Channel will be set according to the individually assigned PD classification
|3-0||MPOL4 - MPOL1||R/W||0||Manual Policing and Foldback configuration bits
0 = The internal device firmware automatically adjusts the Policing (PCUT) and 2xFBn settings based on the assigned class during port turn on
1 = The Policing (PCUT) and 2xFBn settings will not be changed during port turn on.
Note: Independent of these settings, the Policing (PCUT) and 2xFBn settings are returned to their default values upon port turn off.
Note: Setting either bit for a 4P configured port disables the automatic configuration on both channels
The MPOLn bits are cleared upon port turn off.
For 4-pair wired Ports the 2xFBn bits individually control each Channels operation.
Refer to register 0x55h description for more information on additional Foldback and Inrush configuration options