SLVSF02D March   2019  – May 2020 TPS23881

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Simplified Schematic
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
    1.     Pin Functions
    2. 6.1 Detailed Pin Description
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. Parameter Measurement Information
    1. 8.1 Timing Diagrams
  9. Detailed Description
    1. 9.1 Overview
      1. 9.1.1 Operating Modes
        1. 9.1.1.1 Auto
        2. 9.1.1.2 Semiauto
        3. 9.1.1.3 Manual/Diagnostic
        4. 9.1.1.4 Power Off
      2. 9.1.2 PoE Compliance Terminology
      3. 9.1.3 Channel versus Port Terminology
      4. 9.1.4 Requested Class versus Assigned Class
      5. 9.1.5 Power Allocation and Power Demotion
      6. 9.1.6 Programmable SRAM
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Port Remapping
      2. 9.3.2 Port Power Priority
      3. 9.3.3 Analog-to-Digital Converters (ADC)
      4. 9.3.4 I2C Watchdog
      5. 9.3.5 Current Foldback Protection
    4. 9.4 Device Functional Modes
      1. 9.4.1 Detection
      2. 9.4.2 Connection Check
      3. 9.4.3 Classification
      4. 9.4.4 DC Disconnect
    5. 9.5 I2C Programming
      1. 9.5.1 I2C Serial Interface
    6. 9.6 Register Maps
      1. 9.6.1 Complete Register Set
      2. 9.6.2 Detailed Register Descriptions
        1. 9.6.2.1  INTERRUPT Register
          1. Table 6. INTERRUPT Register Field Descriptions
        2. 9.6.2.2  INTERRUPT MASK Register
          1. Table 7. INTERRUPT MASK Register Field Descriptions
        3. 9.6.2.3  POWER EVENT Register
          1. Table 8. POWER EVENT Register Field Descriptions
        4. 9.6.2.4  DETECTION EVENT Register
          1. Table 9. DETECTION EVENT Register Field Descriptions
        5. 9.6.2.5  FAULT EVENT Register
          1. Table 10. FAULT EVENT Register Field Descriptions
        6. 9.6.2.6  START/ILIM EVENT Register
          1. Table 11. START/ILIM EVENT Register Field Descriptions
        7. 9.6.2.7  SUPPLY and FAULT EVENT Register
          1. Table 12. SUPPLY and FAULT EVENT Register Field Descriptions
          2. 9.6.2.7.1 Detected SRAM Faults and "Safe Mode"
            1. 9.6.2.7.1.1 ULA (Ultra Low Alpha) Package Option: TPS23881A
        8. 9.6.2.8  CHANNEL 1 DISCOVERY Register
        9. 9.6.2.9  CHANNEL 2 DISCOVERY Register
        10. 9.6.2.10 CHANNEL 3 DISCOVERY Register
        11. 9.6.2.11 CHANNEL 4 DISCOVERY Register
          1. Table 13. CHANNEL n DISCOVERY Register Field Descriptions
        12. 9.6.2.12 POWER STATUS Register
          1. Table 14. POWER STATUS Register Field Descriptions
        13. 9.6.2.13 PIN STATUS Register
          1. Table 15. PIN STATUS Register Field Descriptions
        14. 9.6.2.14 OPERATING MODE Register
          1. Table 16. OPERATING MODE Register Field Descriptions
        15. 9.6.2.15 DISCONNECT ENABLE Register
          1. Table 20. DISCONNECT ENABLE Register Field Descriptions
        16. 9.6.2.16 DETECT/CLASS ENABLE Register
          1. Table 21. DETECT/CLASS ENABLE Register Field Descriptions
        17. 9.6.2.17 Power Priority / 2Pair PCUT Disable Register Name
          1. Table 22. Power Priority / 2P-PCUT Disable Register Field Descriptions
        18. 9.6.2.18 TIMING CONFIGURATION Register
          1. Table 24. TIMING CONFIGURATION Register Field Descriptions
        19. 9.6.2.19 GENERAL MASK Register
          1. Table 25. GENERAL MASK Register Field Descriptions
        20. 9.6.2.20 DETECT/CLASS RESTART Register
          1. Table 27. DETECT/CLASS RESTART Register Field Descriptions
        21. 9.6.2.21 POWER ENABLE Register
          1. Table 28. POWER ENABLE Register Field Descriptions
        22. 9.6.2.22 RESET Register
          1. Table 32. RESET Register Field Descriptions
        23. 9.6.2.23 ID Register
          1. Table 34. ID Register Field Descriptions
        24. 9.6.2.24 Connection Check and Auto Class Status Register
          1. Table 35. Connection Check and Auto Class Field Descriptions
        25. 9.6.2.25 2-Pair Police Ch-1 Configuration Register
        26. 9.6.2.26 2-Pair Police Ch-2 Configuration Register
        27. 9.6.2.27 2-Pair Police Ch-3 Configuration Register
        28. 9.6.2.28 2-Pair Police Ch-4 Configuration Register
          1. Table 36. 2-Pair Policing Register Fields Descriptions
        29. 9.6.2.29 Capacitance (Legacy PD) Detection
          1. Table 39. Capacitance Detection Register Field Descriptions
        30. 9.6.2.30 Power-on Fault Register
          1. Table 40. Power-on Fault Register Field Descriptions
        31. 9.6.2.31 PORT RE-MAPPING Register
          1. Table 41. PORT RE-MAPPING Register Field Descriptions
        32. 9.6.2.32 Channels 1 and 2 Multi Bit Priority Register
        33. 9.6.2.33 Channels 3 and 4 Multi Bit Priority Register
          1. Table 42. Channels n MBP Register Field Descriptions
        34. 9.6.2.34 4-Pair Wired and Port Power Allocation Register
          1. Table 44. 4-Pair Wired and Power Allocation Register Field Descriptions
        35. 9.6.2.35 4-Pair Police Ch-1 and 2 Configuration Register
        36. 9.6.2.36 4-Pair Police Ch-3 and 4 Configuration Register
          1. Table 46. 4-Pair Police Register Field Descriptions
        37. 9.6.2.37 TEMPERATURE Register
          1. Table 48. TEMPERATURE Register Field Descriptions
        38. 9.6.2.38 4-Pair Fault Configuration Register
          1. Table 49. 4-Pair Fault Register Field Descriptions
        39. 9.6.2.39 INPUT VOLTAGE Register
          1. Table 50. INPUT VOLTAGE Register Field Descriptions
        40. 9.6.2.40 CHANNEL 1 CURRENT Register
        41. 9.6.2.41 CHANNEL 2 CURRENT Register
        42. 9.6.2.42 CHANNEL 3 CURRENT Register
        43. 9.6.2.43 CHANNEL 4 CURRENT Register
          1. Table 51. CHANNEL n CURRENT Register Field Descriptions
        44. 9.6.2.44 CHANNEL 1 VOLTAGE Register
        45. 9.6.2.45 CHANNEL 2 VOLTAGE Register
        46. 9.6.2.46 CHANNEL 3 VOLTAGE Register
        47. 9.6.2.47 CHANNEL 4 VOLTAGE Register
          1. Table 52. CHANNEL n VOLTAGE Register Field Descriptions
        48. 9.6.2.48 2x FOLDBACK SELECTION Register
          1. Table 53. 2x FOLDBACK SELECTION Register Field Descriptions
        49. 9.6.2.49 FIRMWARE REVISION Register
          1. Table 54. FIRMWARE REVISION Register Field Descriptions
        50. 9.6.2.50 I2C WATCHDOG Register
          1. Table 55. I2C WATCHDOG Register Field Descriptions
        51. 9.6.2.51 DEVICE ID Register
          1. Table 57. DEVICE ID Register Field Descriptions
        52. 9.6.2.52 CHANNEL 1 DETECT RESISTANCE Register
        53. 9.6.2.53 CHANNEL 2 DETECT RESISTANCE Register
        54. 9.6.2.54 CHANNEL 3 DETECT RESISTANCE Register
        55. 9.6.2.55 CHANNEL 4 DETECT RESISTANCE Register
          1. Table 58. DETECT RESISTANCE Register Fields Descriptions
        56. 9.6.2.56 CHANNEL 1 DETECT CAPACITANCE Register
        57. 9.6.2.57 CHANNEL 2 DETECT CAPACITANCE Register
        58. 9.6.2.58 CHANNEL 3 DETECT CAPACITANCE Register
        59. 9.6.2.59 CHANNEL 4 DETECT CAPACITANCE Register
          1. Table 59. DETECT CAPACITANCE Register Fields Descriptions
        60. 9.6.2.60 CHANNEL 1 ASSIGNED CLASS Register
        61. 9.6.2.61 CHANNEL 2 ASSIGNED CLASS Register
        62. 9.6.2.62 CHANNEL 3 ASSIGNED CLASS Register
        63. 9.6.2.63 CHANNEL 4 ASSIGNED CLASS Register
          1. Table 60. CHANNEL n ASSIGNED CLASS Register Field Descriptions
        64. 9.6.2.64 AUTO CLASS CONTROL Register
          1. Table 63. AUTO CLASS CONTROL Register Field Descriptions
        65. 9.6.2.65 CHANNEL 1 AUTO CLASS POWER Register
        66. 9.6.2.66 CHANNEL 2 AUTO CLASS POWER Register
        67. 9.6.2.67 CHANNEL 3 AUTO CLASS POWER Register
        68. 9.6.2.68 CHANNEL 4 AUTO CLASS POWER Register
          1. Table 65. AUTO CLASS POWER Register Fields Descriptions
        69. 9.6.2.69 ALTERNATIVE FOLDBACK Register
          1. Table 66. ALTERNATIVE FOLDBACK Register Field Descriptions
        70. 9.6.2.70 SRAM CONTROL Register
          1. Table 67.  SRAM CONTROL Register Field Descriptions
          2. 9.6.2.70.1 SRAM START ADDRESS (LSB) Register
          3. 9.6.2.70.2 SRAM START ADDRESS (MSB) Register
            1. Table 68. SRAM START ADDRESS Register Field Descriptions
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Introduction to PoE
        1. 10.1.1.1 2-Pair Versus 4-Pair Power and the New IEEE802.3bt Standard
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Connections on Unused Channels
        2. 10.2.2.2 Power Pin Bypass Capacitors
        3. 10.2.2.3 Per Port Components
        4. 10.2.2.4 System Level Components (not shown in the schematic diagrams)
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
    1. 11.1 VDD
    2. 11.2 VPWR
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Kelvin Current Sensing Resistors
    2. 12.2 Layout Example
      1. 12.2.1 Component Placement and Routing Guidelines
        1. 12.2.1.1 Power Pin Bypass Capacitors
        2. 12.2.1.2 Per-Port Components
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Support Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Complete Register Set

Table 4. Main Registers

Cmd Code Register or
Command Name
I2C
R/W
Data
Byte
RST State Bits Description
INTERRUPTS
00h INTERRUPT RO 1 1000,0000b(1) SUPF STRTF IFAULT CLASC DETC DISF PGC PEC
01h INTERRUPT MASK R/W 1 1000,0000b
SUMSK STMSK IFMSK CLMSK DEMSK DIMSK PGMSK PEMSK
EVENT
02h POWER EVENT RO 1 0000,0000b Power Good status change Power Enable status change
03h CoR 1 PGC4 PGC3 PGC2 PGC1 PEC4 PEC3 PEC2 PEC1
04h DETECTION EVENT RO 1 0000,0000b Classification Detection
05h CoR 1 CLSC4 CLSC3 CLSC2 CLSC1 DETC4 DETC3 DETC2 DETC1
06h FAULT EVENT RO 1 0000,0000b Disconnect occurred PCUT fault occurred
07h CoR 1 DISF4 DISF3 DISF2 DISF1 PCUT4 PCUT3 PCUT2 PCUT1
08h START/ILIM EVENT RO 1 0000,0000b ILIM fault occurred START fault occurred
09h CoR 1 ILIM4 ILIM3 ILIM2 ILIM1 STRT4 STRT3 STRT2 STRT1
0Ah SUPPLY/FAULT EVENT RO 1 0111,0000b(2) TSD VDUV VDWRN VPUV PCUT34 PCUT12 OSSE RAMFLT
0Bh CoR 1
STATUS
0Ch CHANNEL 1 DISCOVERY RO 1 0000,0000b Requested CLASS Channel 1 DETECT Channel 1
0Dh CHANNEL 2 DISCOVERY RO 1 0000,0000b Requested CLASS Channel 2 DETECT Channel 2
0Eh CHANNEL 3 DISCOVERY RO 1 0000,0000b Requested CLASS Channel 3 DETECT Channel 3
0Fh CHANNEL 4 DISCOVERY RO 1 0000,0000b Requested CLASS Channel 4 DETECT Channel 4
10h POWER STATUS RO 1 0000,0000b PG4 PG3 PG2 PG1 PE4 PE3 PE2 PE1
11h PIN STATUS RO 1 0,A[4:0],0,0 Rsvd SLA4 SLA3 SLA2 SLA1 SLA0 Rsvd Rsvd
CONFIGURATION
12h OPERATING MODE R/W 1 0000,0000b Channel 4 Mode Channel 3 Mode Channel 2 Mode Channel 1 Mode
13h DISCONNECT ENABLE R/W 1 0000 ,1111b Rsvd Rsvd Rsvd Rsvd DCDE4 DCDE3 DCDE2 DCDE1
14h DETECT/CLASS ENABLE R/W 1 0000,0000b CLE4 CLE3 CLE2 CLE1 DETE4 DETE3 DETE2 DETE1
15h PWRPR/PCUT DISABLE R/W 1 0000,0000b OSS4 OSS3 OSS2 OSS1 DCUT4 DCUT3 DCUT2 DCUT1
16h TIMING CONFIG R/W 1 0000,0000b TLIM TSTART TOVLD TMPDO
17h GENERAL MASK R/W 1 1000,0000b INTEN Rsvd nbitACC MbitPrty CLCHE DECHE Rsvd
PUSH BUTTONS
18h DETECT/CLASS Restart WO 1 0000,0000b RCL4 RCL3 RCL2 RCL1 RDET4 RDET3 RDET2 RDET1
19h POWER ENABLE WO 1 0000,0000b POFF4 POFF3 POFF2 POFF1 PWON4 PWON3 PWON2 PWON1
1Ah RESET WO 1 0000,0000b CLRAIN CLINP Rsvd RESAL RESP4 RESP3 RESP2 RESP1
GENERAL/SPECIALIZED
1Bh ID RO 1 0101,0101b MFR ID IC Version
1Ch AUTOCLASS and CONNECTION CHECK RO 1 0000,0000b AC4 AC3 AC2 AC1 CC34_2 CC34_1 CC12_2 CC12_1
1Dh RESERVED R/W 1 0000,0000b Rsrvd
1Eh 2P POLICE 1 CONFIG R/W 1 1111,1111b 2-Pair POLICE Channel 1
1Fh 2P POLICE 2 CONFIG R/W 1 1111,1111b 2-Pair POLICE Channel 2
20h 2P POLICE 3 CONFIG R/W 1 1111,1111b 2-Pair POLICE Channel 3
21h 2P POLICE 4CONFIG R/W 1 1111,1111b 2-Pair POLICE Channel 4
22h CAP MEASUREMENT(3) R/W 1 0000,0000b Rsvd CDET4 Rsvd CDET3 Rsvd CDET2 Rsvd CDET1
23h Reserved R/W 1 0000,0000b Rsvd Rsvd Rsvd Rsvd Rsvd Rsvd Rsvd Rsvd
24h Power-on FAULT RO 1 0000,0000b PF Channel 4 PF Channel 3 PF Channel 2 PF Channel 1
25h CoR 1
26h RE-MAPPING R/W 1 1110,0100b Physical re-map Logical Port 4 Physical re-map Logical Port 3 Physical re-map Logical Port 2 Physical re-map Logical Port 1
27h Multi-Bit Priority 21 R/W 1 0000,0000b Rsvd Channel 2 Rsvd Channel 1
28h Multi-Bit Priority 43 R/W 1 0000,0000b Rsvd Channel 4 Rsvd Channel 3
29h Port Power Allocation R/W 1 0000,0000b 4P34 MC34 4P12 MC12
2Ah 4P POLICE 12 CONFIG R/W 1 1111,1111b 4-Pair POLICE Channels 1 and 2
2Bh 4P POLICE 34 CONFIG R/W 1 1111,1111b 4-Pair POLICE Channels 3 and 4
2Ch TEMPERATURE RO 1 0000,0000b Temperature (bits 7 to 0)
2Dh 4P FAULT CONFIG R/W 1 0000,0000b NLM34 NLM12 NCT34 NCT12 4PPCT34 4PPCT12 DCDT34 DCDT12
2Eh INPUT VOLTAGE RO 2 0000,0000b Input Voltage: LSByte
2Fh RO 0000,0000b Rsvd Rsvd Input Voltage: MSByte (bits 13 to 8)
EXTENDED REGISTER SET – PARAMETRIC MEASUREMENT
30h Channel 1 CURRENT RO 2 0000,0000b Channel 1 Current: LSByte
31h RO 0000,0000b Rsvd Rsvd Channel 1 Current: MSByte (bits 13 to 8)
32h Channel 1 VOLTAGE RO 2 0000,0000b Channel 1 Voltage: LSByte
33h RO 0000,0000b Rsvd Rsvd Channel 1 Voltage: MSByte (bits 13 to 8)
SUPF bit reset state shown is at Power up only
VDUV, VPUV and VDWRN bits reset state shown is at Power up only
Capacitance Measurement is only supported if SRAM code is programmed

Table 5. Main Registers

Cmd Code Register or
Command Name
I2C R/W Data Byte RST State Bits Description
34h Channel 2 CURRENT RO 2 0000,0000b Channel 2 Current: LSByte
35h RO 0000,0000b Rsvd Rsvd Channel 2 Current: MSByte (bits 13 to 8)
36h Channel 2 VOLTAGE RO 2 0000,0000b Channel 2 Voltage: LSByte
37h RO 0000,0000b Rsvd Rsvd Channel 2 Voltage: MSByte (bits 13 to 8)
38h Channel 3 CURRENT RO 2 0000,0000b Channel 3 current: LSByte
39h RO 0000,0000b Rsvd Rsvd Channel 3 Current: MSByte (bits 13 to 8)
3Ah Channel 3 VOLTAGE RO 2 0000,0000b Channel 3 Voltage: LSByte
3Bh RO 0000,0000b Rsvd Rsvd Channel 3 Voltage: MSByte (bits 13 to 8)
3Ch Channel 4 CURRENT RO 2 0000,0000b Channel 4 current: LSByte
3Dh RO 0000,0000b Rsvd Rsvd Channel 4 Current: MSByte (bits 13 to 8)
3Eh Channel 4 VOLTAGE RO 2 0000,0000b Channel 4 Voltage: LSByte
3Fh RO 0000,0000b Rsvd Rsvd Channel 4 Voltage: MSByte (bits 13 to 8)
CONFIGURATION/OTHERS
40h CHANNEL FOLDBACK R/W 1 0000,0000b 2xFB4 2xFB3 2xFB2 2xFB1 Rsvd Rsvd Rsvd Rsvd
41h FIRMWARE REVISION RO 1 RRRR,RRRRb Firmware Revision
42h I2C WATCHDOG R/W 1 0001,0110b Rsvd Rsvd Rsvd Watchdog Disable WDS
43h DEVICE ID RO 1 0010,0010b Device ID number Silicon Revision number
SIGNATURE MEASUREMENTS
44h Ch1 DETECT RESISTANCE RO 1 0000,0000b Channel 1 Resistance
45h Ch2 DETECT RESISTANCE RO 1 0000,0000b Channel 2 Resistance
46h Ch3 DETECT RESISTANCE RO 1 0000,0000b Channel 3 Resistance
47h Ch4 DETECT RESISTANCE RO 1 0000,0000b Channel 4 Resistance
48h Ch1 CAP MEASUREMENT(3) RO 1 0000,0000b Channel 1 Capacitance
49h Ch2 CAP MEASUREMENT(3) RO 1 0000,0000b Channel 2 Capacitance
4Ah Ch3 CAP MEASUREMENT(3) RO 1 0000,0000b Channel 3 Capacitance
4Bh Ch4 CAP MEASUREMENT(3) RO 1 0000,0000b Channel 4 Capacitance
ASSIGNED CHANNEL STATUS
4Ch ASSIGNED CLASS CHANNEL 1 RO 1 0000,0000b Assigned CLASS Channel 1 Previous CLASS Channel 1
4Dh ASSIGNED CLASS CHANNEL 2 RO 1 0000,0000b Assigned CLASS Channel 2 Previous CLASS Channel 2
4Eh ASSIGNED CLASS CHANNEL 3 RO 1 0000,0000b Assigned CLASS Channel 3 Previous CLASS Channel 3
4Fh ASSIGNED CLASS CHANNEL 4 RO 1 0000,0000b Assigned CLASS Channel 4 Previous CLASS Channel 4
AUTOCLASS CONFIGURATION/MEASUREMENTS
50h AUTOCLASS CONTROL R/W 1 0000,0000b MAC4 MAC3 MAC2 MAC1 AAC4 AAC3 AAC2 AAC1
51h CHANNEL 1 AUTOCLASS PWR RO 1 0000,0000b Rsrvd Channel 1 AutoClass Power
52h CHANNEL 2 AUTOCLASS PWR RO 1 0000,0000b Rsrvd Channel 2 AutoClass Power
53h CHANNEL 3 AUTOCLASS PWR RO 1 0000,0000b Rsrvd Channel 3 AutoClass Power
54h CHANNEL 4 AUTOCLASS PWR RO 1 0000,0000b Rsrvd Channel 4 AutoClass Power
MISCELLANEOUS
55h ALTERNATIVE FOLDBACK R/W 1 0000,0000b ALTFB4 ALTFB3 ALTFB2 ALTFB1 ALTIR4 ALTIR3 ALTIR2 ALTIR1
56h - 5Fh RESERVED R/W 1 0000,0000b Rsrvd Rsrvd Rsrvd Rsrvd Rsrvd Rsrvd Rsrvd Rsrvd
SRAM
60h SRAM CONTROL R/W 1 0000,0000b PROG_SEL CPU_RST Rsrvd PAR_EN RAM_EN PAR_SEL RZ/W CLR_PTR
61h SRAM DATA R/W - - SRAM DATA - Read and Write (continuous)
62h START ADDRESS R/W 1 0000,0000b Programming Start Address (LSB)
63h R/W 1 0000,0000b Programming Start Address (MSB)
64h - 6Fh RESERVED R/W 1 0000,0000b Rsrvd Rsrvd Rsrvd Rsrvd Rsrvd Rsrvd Rsrvd Rsrvd