SLVSF02D March 2019 – May 2020 TPS23881
COMMAND = 13h with 1 Data Byte, Read/Write
Bit Descriptions: Defines the disconnect detection mechanism for each channel.
|LEGEND: R/W = Read/Write; R = Read only; -n = value after reset|
|3–0||DCDE4–DCDE1||R/W||1||DC disconnect enable
1 = DC Disconnect Enabled
0 = DC Disconnect Disabled
Look at the TIMING CONFIGURATION register for more details on how to define the TDIS time period.
DC disconnect consists in measuring the Channel DC current at SENn, starting a timer (TDIS) if this current is below a threshold and turning the Channel off if a time-out occurs. Also, the corresponding disconnect bit (DISFn) in the FAULT EVENT register is set accordingly. The TDIS counter is reset each time the current rises above the disconnect threshold for at least 3 msec. The counter does not decrement below zero.
For 4P Single signature devices, if either DCDEx bit is set, both channels will be shut off when the disconnect timer expires.
In the event a singular channel of a 4-pair dual signature PD is turned off due to a disconnect fault or other reason, power may be reapplied to that channel by setting the PWON bit in 0x19h provided the detection and classification are still valid and the Power Allocation settings in 0x29 are sufficient based on the assigned classification of the powered channel.
The DCDTnn bits in 0x2D set the disconnect threshold.
The DCDTnn bits are automatically configured during turn on based on the 4PWnn bits in 0x29 and the Assigned classification results (0x4C-4F) based on IEEE compliance requirements.