SLVSF02D March   2019  – May 2020 TPS23881

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Simplified Schematic
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
    1.     Pin Functions
    2. 6.1 Detailed Pin Description
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. Parameter Measurement Information
    1. 8.1 Timing Diagrams
  9. Detailed Description
    1. 9.1 Overview
      1. 9.1.1 Operating Modes
        1. 9.1.1.1 Auto
        2. 9.1.1.2 Semiauto
        3. 9.1.1.3 Manual/Diagnostic
        4. 9.1.1.4 Power Off
      2. 9.1.2 PoE Compliance Terminology
      3. 9.1.3 Channel versus Port Terminology
      4. 9.1.4 Requested Class versus Assigned Class
      5. 9.1.5 Power Allocation and Power Demotion
      6. 9.1.6 Programmable SRAM
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Port Remapping
      2. 9.3.2 Port Power Priority
      3. 9.3.3 Analog-to-Digital Converters (ADC)
      4. 9.3.4 I2C Watchdog
      5. 9.3.5 Current Foldback Protection
    4. 9.4 Device Functional Modes
      1. 9.4.1 Detection
      2. 9.4.2 Connection Check
      3. 9.4.3 Classification
      4. 9.4.4 DC Disconnect
    5. 9.5 I2C Programming
      1. 9.5.1 I2C Serial Interface
    6. 9.6 Register Maps
      1. 9.6.1 Complete Register Set
      2. 9.6.2 Detailed Register Descriptions
        1. 9.6.2.1  INTERRUPT Register
          1. Table 6. INTERRUPT Register Field Descriptions
        2. 9.6.2.2  INTERRUPT MASK Register
          1. Table 7. INTERRUPT MASK Register Field Descriptions
        3. 9.6.2.3  POWER EVENT Register
          1. Table 8. POWER EVENT Register Field Descriptions
        4. 9.6.2.4  DETECTION EVENT Register
          1. Table 9. DETECTION EVENT Register Field Descriptions
        5. 9.6.2.5  FAULT EVENT Register
          1. Table 10. FAULT EVENT Register Field Descriptions
        6. 9.6.2.6  START/ILIM EVENT Register
          1. Table 11. START/ILIM EVENT Register Field Descriptions
        7. 9.6.2.7  SUPPLY and FAULT EVENT Register
          1. Table 12. SUPPLY and FAULT EVENT Register Field Descriptions
          2. 9.6.2.7.1 Detected SRAM Faults and "Safe Mode"
            1. 9.6.2.7.1.1 ULA (Ultra Low Alpha) Package Option: TPS23881A
        8. 9.6.2.8  CHANNEL 1 DISCOVERY Register
        9. 9.6.2.9  CHANNEL 2 DISCOVERY Register
        10. 9.6.2.10 CHANNEL 3 DISCOVERY Register
        11. 9.6.2.11 CHANNEL 4 DISCOVERY Register
          1. Table 13. CHANNEL n DISCOVERY Register Field Descriptions
        12. 9.6.2.12 POWER STATUS Register
          1. Table 14. POWER STATUS Register Field Descriptions
        13. 9.6.2.13 PIN STATUS Register
          1. Table 15. PIN STATUS Register Field Descriptions
        14. 9.6.2.14 OPERATING MODE Register
          1. Table 16. OPERATING MODE Register Field Descriptions
        15. 9.6.2.15 DISCONNECT ENABLE Register
          1. Table 20. DISCONNECT ENABLE Register Field Descriptions
        16. 9.6.2.16 DETECT/CLASS ENABLE Register
          1. Table 21. DETECT/CLASS ENABLE Register Field Descriptions
        17. 9.6.2.17 Power Priority / 2Pair PCUT Disable Register Name
          1. Table 22. Power Priority / 2P-PCUT Disable Register Field Descriptions
        18. 9.6.2.18 TIMING CONFIGURATION Register
          1. Table 24. TIMING CONFIGURATION Register Field Descriptions
        19. 9.6.2.19 GENERAL MASK Register
          1. Table 25. GENERAL MASK Register Field Descriptions
        20. 9.6.2.20 DETECT/CLASS RESTART Register
          1. Table 27. DETECT/CLASS RESTART Register Field Descriptions
        21. 9.6.2.21 POWER ENABLE Register
          1. Table 28. POWER ENABLE Register Field Descriptions
        22. 9.6.2.22 RESET Register
          1. Table 32. RESET Register Field Descriptions
        23. 9.6.2.23 ID Register
          1. Table 34. ID Register Field Descriptions
        24. 9.6.2.24 Connection Check and Auto Class Status Register
          1. Table 35. Connection Check and Auto Class Field Descriptions
        25. 9.6.2.25 2-Pair Police Ch-1 Configuration Register
        26. 9.6.2.26 2-Pair Police Ch-2 Configuration Register
        27. 9.6.2.27 2-Pair Police Ch-3 Configuration Register
        28. 9.6.2.28 2-Pair Police Ch-4 Configuration Register
          1. Table 36. 2-Pair Policing Register Fields Descriptions
        29. 9.6.2.29 Capacitance (Legacy PD) Detection
          1. Table 39. Capacitance Detection Register Field Descriptions
        30. 9.6.2.30 Power-on Fault Register
          1. Table 40. Power-on Fault Register Field Descriptions
        31. 9.6.2.31 PORT RE-MAPPING Register
          1. Table 41. PORT RE-MAPPING Register Field Descriptions
        32. 9.6.2.32 Channels 1 and 2 Multi Bit Priority Register
        33. 9.6.2.33 Channels 3 and 4 Multi Bit Priority Register
          1. Table 42. Channels n MBP Register Field Descriptions
        34. 9.6.2.34 4-Pair Wired and Port Power Allocation Register
          1. Table 44. 4-Pair Wired and Power Allocation Register Field Descriptions
        35. 9.6.2.35 4-Pair Police Ch-1 and 2 Configuration Register
        36. 9.6.2.36 4-Pair Police Ch-3 and 4 Configuration Register
          1. Table 46. 4-Pair Police Register Field Descriptions
        37. 9.6.2.37 TEMPERATURE Register
          1. Table 48. TEMPERATURE Register Field Descriptions
        38. 9.6.2.38 4-Pair Fault Configuration Register
          1. Table 49. 4-Pair Fault Register Field Descriptions
        39. 9.6.2.39 INPUT VOLTAGE Register
          1. Table 50. INPUT VOLTAGE Register Field Descriptions
        40. 9.6.2.40 CHANNEL 1 CURRENT Register
        41. 9.6.2.41 CHANNEL 2 CURRENT Register
        42. 9.6.2.42 CHANNEL 3 CURRENT Register
        43. 9.6.2.43 CHANNEL 4 CURRENT Register
          1. Table 51. CHANNEL n CURRENT Register Field Descriptions
        44. 9.6.2.44 CHANNEL 1 VOLTAGE Register
        45. 9.6.2.45 CHANNEL 2 VOLTAGE Register
        46. 9.6.2.46 CHANNEL 3 VOLTAGE Register
        47. 9.6.2.47 CHANNEL 4 VOLTAGE Register
          1. Table 52. CHANNEL n VOLTAGE Register Field Descriptions
        48. 9.6.2.48 2x FOLDBACK SELECTION Register
          1. Table 53. 2x FOLDBACK SELECTION Register Field Descriptions
        49. 9.6.2.49 FIRMWARE REVISION Register
          1. Table 54. FIRMWARE REVISION Register Field Descriptions
        50. 9.6.2.50 I2C WATCHDOG Register
          1. Table 55. I2C WATCHDOG Register Field Descriptions
        51. 9.6.2.51 DEVICE ID Register
          1. Table 57. DEVICE ID Register Field Descriptions
        52. 9.6.2.52 CHANNEL 1 DETECT RESISTANCE Register
        53. 9.6.2.53 CHANNEL 2 DETECT RESISTANCE Register
        54. 9.6.2.54 CHANNEL 3 DETECT RESISTANCE Register
        55. 9.6.2.55 CHANNEL 4 DETECT RESISTANCE Register
          1. Table 58. DETECT RESISTANCE Register Fields Descriptions
        56. 9.6.2.56 CHANNEL 1 DETECT CAPACITANCE Register
        57. 9.6.2.57 CHANNEL 2 DETECT CAPACITANCE Register
        58. 9.6.2.58 CHANNEL 3 DETECT CAPACITANCE Register
        59. 9.6.2.59 CHANNEL 4 DETECT CAPACITANCE Register
          1. Table 59. DETECT CAPACITANCE Register Fields Descriptions
        60. 9.6.2.60 CHANNEL 1 ASSIGNED CLASS Register
        61. 9.6.2.61 CHANNEL 2 ASSIGNED CLASS Register
        62. 9.6.2.62 CHANNEL 3 ASSIGNED CLASS Register
        63. 9.6.2.63 CHANNEL 4 ASSIGNED CLASS Register
          1. Table 60. CHANNEL n ASSIGNED CLASS Register Field Descriptions
        64. 9.6.2.64 AUTO CLASS CONTROL Register
          1. Table 63. AUTO CLASS CONTROL Register Field Descriptions
        65. 9.6.2.65 CHANNEL 1 AUTO CLASS POWER Register
        66. 9.6.2.66 CHANNEL 2 AUTO CLASS POWER Register
        67. 9.6.2.67 CHANNEL 3 AUTO CLASS POWER Register
        68. 9.6.2.68 CHANNEL 4 AUTO CLASS POWER Register
          1. Table 65. AUTO CLASS POWER Register Fields Descriptions
        69. 9.6.2.69 ALTERNATIVE FOLDBACK Register
          1. Table 66. ALTERNATIVE FOLDBACK Register Field Descriptions
        70. 9.6.2.70 SRAM CONTROL Register
          1. Table 67.  SRAM CONTROL Register Field Descriptions
          2. 9.6.2.70.1 SRAM START ADDRESS (LSB) Register
          3. 9.6.2.70.2 SRAM START ADDRESS (MSB) Register
            1. Table 68. SRAM START ADDRESS Register Field Descriptions
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Introduction to PoE
        1. 10.1.1.1 2-Pair Versus 4-Pair Power and the New IEEE802.3bt Standard
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Connections on Unused Channels
        2. 10.2.2.2 Power Pin Bypass Capacitors
        3. 10.2.2.3 Per Port Components
        4. 10.2.2.4 System Level Components (not shown in the schematic diagrams)
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
    1. 11.1 VDD
    2. 11.2 VPWR
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Kelvin Current Sensing Resistors
    2. 12.2 Layout Example
      1. 12.2.1 Component Placement and Routing Guidelines
        1. 12.2.1.1 Power Pin Bypass Capacitors
        2. 12.2.1.2 Per-Port Components
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Support Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Electrical Characteristics

Conditions are –40 < T< 125 °C unless otherwise noted. VVDD = 3.3 V,VVPWR = 54 V, VDGND = VAGND,DGND, KSENSA, KSENSB, KSENSC and KSENSD connected to AGND, and all outputs are unloaded, 2xFBn =0.  Positive currents are into pins.  RSENSE = 0.200 Ω, to KSENSA (SEN1 orSEN2), to KSENSB (SEN3 or SEN4), to KSENSC (SEN5 or SEN6) or to KSENSD (SEN7 or SEN8). Typical values are at 25 °C. All voltages are with respect to AGND unless otherwise noted. Operating registers loaded with default values unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT SUPPLY VPWR
IVPWR VPWR Current consumption VVPWR = 54 V 10 12.5 mA
VUVLOPW_F VPWR UVLO falling threshold Check internal oscillator stops operating 14.5 17.5 V
VUVLOPW_R VPWR UVLO rising threshold 15.5 18.5 V
VPUV_F VPWR Undervoltage falling threshold VPUV threshold 25 26.5 28 V
INPUT SUPPLY VDD
IVDD VDD Current consumption 6 12 mA
VUVDD_F VDD UVLO falling threshold For channel deassertion 2.1 2.25 2.4 V
VUVDD_R VDD UVLO rising threshold 2.45 2.6 2.75 V
VUVDD_HYS Hysteresis VDD UVLO 0.35 V
VUVW_F VDD UVLO warning threshold VDD falling 2.6 2.8 3 V
A/D CONVERTERS
TCONV_I Conversion time All ranges, each channel 0.64 0.8 0.96 ms
TCONV_V Conversiontime All ranges, each channel 0.82 1.03 1.2 ms
TINT_CUR Integration time, Current Each channel, channel ON current 82 102 122 ms
TINT_DET Integration time, Detection 13.1 16.6 20 ms
TINT_channelV Integration time, Channel Voltage channel powered 3.25 4.12 4.9 ms
TINT_inV Integration time, Input Voltage 3.25 4.12 4.9 ms
Input voltage conversion scale factor and accuracy VVPWR = 57 V 15175 15565 15955 Counts
55.57 57 58.43 V
VVPWR = 44 V 11713 12015 12316 Counts
42.89 44 45.10 V
Powered Channel voltage conversion scale factor and accuracy VVPWR - VDRAINn = 57 V 15175 15565 15955 Counts
55.57 57 58.43 V
VVPWR - VDRAINn = 44 V 11713 12015 12316 Counts
42.89 44 45.10 V
δV/VChannel Voltage reading accuracy –2.5 2.5 %
Powered Channel current conversion scale factor and accuracy Channel current = 770 mA 8431 8604 8776 Counts
754.5 770 785.4 mA
Channel Current = 100 mA 1084 1118 1152 Counts
97 100 103 mA
δI/IChannel Current reading accuracy Channel Current =100 mA –3 3 %
Channel Current =770 mA –2 2
Powered Channel current ful scale output Channel currents = 1.5 A, 2xFBn = 1 14959 15671 Counts
1.34 1.400 A
σI Current Reading Repeatability Full Scale reading –7.5 7.5 mA
δR/RChannel Resistance reading accuracy 15 kΩ ≤ RChannel ≤ 33 kΩ, CChannel ≤ 0.25 µF –7 7 %
Ibias Sense Pin bias current Channel ON or during class –2.5 0 µA
GATE 1-8
VGOH Gate drive voltage VGATEn , IGATE = -1 µA 10 12.5 V
IGO- Gate sinking current with Power-on Reset, OSS detected or channel turnoff command VGATEn = 5 V 60 100 190 mA
IGO short- Gate sinking current with channel short-circuit VGATEn = 5 V,
VSENn  ≥ Vshort (or Vshort2X if 2X mode)
60 100 190 mA
IGO+ Gate sourcing current VGATEn = 0 V, default selection 39 50 63 µA
tD_off_OSS Gate turnoff time from 1-bit OSS input From OSS to VGATEn < 1 V,
VSENn = 0 V, MbitPrty = 0
1 5 µs
tOSS_OFF Gate turnoff time from 3-bit OSS input From Start bit falling edge to VGATEn < 1 V,
VSENn = 0 V, MbitPrty = 1
72 104 µs
tP_off_CMD Gate turnoff time from channel turnoff command From Channel off command (POFFn = 1) to VGATEn < 1 V, VSENn = 0 V 300 µs
tP_off_RST Gate turnoff time with /RESET From /RESET low to VGATEn < 1 V, VSENn = 0 V 1 5 µs
DRAIN 1-8
VPGT Power-Good threshold Measured at VDRAINn 1 2.13 3 V
VSHT Shorted FET threshold Measured at VDRAINn 4 6 8 V
RDRAIN Resistance from DRAINn to VPWR Any operating mode except during detection or while the Channel is ON, including in device RESET state 80 100 190
AUTOCLASS
tClass_ACS Start of Autoclass Detection Measured from the start of Class 90 100 ms
tAUTO_PSE1 Start of Autoclass Power Measurement Measured from the end of Inrush 1.4 1.6 s
Measured from setting the MACx bit while channel is already powered 10 ms
tAUTO Duration of Autoclass Power Measurement 1.7 1.8 1.9 s
tAUTO_window Autoclass Power Measurement Sliding Window 0.15 0.3 s
PAC Autoclass Channel Power conversion scale factor and accuracy VPWR = 52 V, VDRAINn = 0 V,
Channel current = 770 mA
76 80 84 Counts
VPWR = 50 V, VDRAINn = 0 V,
Channel current = 100 mA
9 10 11
DETECTION
IDISC Detection current First and 3rd detection points
VVPWR - VDRAINn = 0 V
145 160 190 µA
2nd and 4th detection points VVPWR - VDRAINn = 0 V 235 270 300
ΔIDISC 2nd – 1st detection currents VVPWR - VDRAINn = 0 V 98 110 118 µA
Vdet_open Open circuit detection voltage Measured as VVPWR - VDRAINn 23.5 26 29 V
RREJ_LOW Rejected resistance low range 0.86 15
RREJ_HI Rejected resistance high range 33 100
RACCEPT Accepted resistance range 19 25 26.5
RSHORT Shorted Channel threshold 360 Ω
ROPEN Open Channel Threshold 400
tDET Detection Duration Time to complete a detection, 4Pxx = 0 275 350 425 ms
tCC Connection Check Duration Time to complete connection check after a valid detection, 4Pxx = 1 150 400 ms
tDET_BOFF Detect backoff pause between discovery attempts VVPWR - VDRAINn > 2.5 V 300 400 500 ms
VVPWR - VDRAINn < 2.5 V 20 100 ms
tDET_DLY Detection delay From command or PD attachment to Channel detection complete 4Pxx = 0 590 ms
Capactance Measurement Cport = 10uF 8.5 10 11.5 uF
CLASSIFICATION
VCLASS Classification Voltage VVPWR - VDRAINn, VSENn ≥ 0 mV
Ichannel ≥ 180 µA
15.5 18.5 20.5 V
ICLASS_Lim Classification Current Limit VVPWR - VDRAINn = 0 V 65 75 90 mA
ICLASS_TH Classification Threshold Current Class 0-1 5 8 mA
Class 1-2 13 16 mA
Class 2-3 21 25 mA
Class 3-4 31 35 mA
Class 4-Class overcurrent 45 51 mA
tLCE Classification Duration (1st Finger) From detection complete 95 105 ms
tCLE2-5 Classification Duration (2nd- 5th Finger) From Mark complete 6.5 12 ms
MARK
VMARK Mark Voltage 4 mA ≥ IChannel ≥ 180 µA
VVPWR - VDRAINn
7 10 V
IMARK_Lim Mark Sinking Current Limit VVPWR - VDRAINn = 0 V 60 75 90 mA
tME Mark Duration 6 12 ms
DC DISCONNECT
VIMIN DC disconnect threshold DCDTxx = 0 0.8 1.3 1.8 mV
DCDTxx = 1 0.4 0.9 1.4 mV
tMPDO PD Maintain Power signature dropout time limit TMPDO = 00 320 400 ms
TMPDO = 01 75 100 ms
TMPDO = 10 150 200 ms
TMPDO = 11 600 800 ms
tMPS PD Maintain Power Signature time for validity 2.5 3 ms
PORT POWER POLICING
δPCUT/PCUT PCUT tolerance POL ≤ 15W 0 5 10 %
δPCUT/PCUT PCUT tolerance 15W < POL < 90W 0 3 6 %
δPCUT/PCUT PCUT tolerance POL ≥ 90W 0 2.5 5 %
tOVLD PCUT time limit TOVLD = 00 50 70 ms
TOVLD = 01 25 35
TOVLD = 10 100 140
TOVLD = 11 200 280
PORT CURRENT INRUSH
VInrush IInrush limit, ALTIRNn = 0 VVPWR - VDRAINn = 1 V 19 30 41 mV
VVPWR - VDRAINn = 10 V 19 30 41
VVPWR - VDRAINn = 15 V 33 44 55
VVPWR - VDRAINn = 30 V 80 90
VVPWR - VDRAINn = 55 V 80 90
IInrush limit, ALTIRNn = 1 VVPWR - VDRAINn = 1 V 19 30 41
VVPWR - VDRAINn = 10 V 36 47 58
VVPWR - VDRAINn = 15 V 53 64 75
VVPWR - VDRAINn = 30 V 80 90
VVPWR - VDRAINn = 55 V 80 90
tSTART Maximum current limit duration in start-up TSTART = 00 50 70 ms
TSTART = 01 25 35
TSTART = 10 100 140
PORT CURRENT FOLDBACK
VLIM ILIM 1X limit, 2xFB = 0 and ALTFBn = 0 VDRAINn = 1 V 80 90 mV
VDRAINn = 15 V 80 90
VDRAINn = 30 V 51 58 65
VDRAINn = 50 V 23 30 37
ILIM 1X limit, 2xFB = 0 and ALTFBn = 1 VDRAINn = 1 V 80 90
VDRAINn = 25 V 80 90
VDRAINn = 40 V 45 51 57
VDRAINn = 50 V 23 30 37
VLIM2X ILIM 2X limit, 2xFB = 1 and ALTFBn = 0 VDRAINn = 1 V 245 250 262 mV
VDRAINn = 10 V 164 180 196
VDRAINn = 30 V 51 58 64
VDRAINn = 50 V 23 30 37
ILIM 2X limit, 2xFB = 1 and ALTFBn = 1 VDRAINn = 1 V 245 250 262
VDRAINn = 20 V 139 147 155
VDRAINn = 40 V 45 51 57
VDRAINn = 50 V 23 30 37
tLIM ILIM time limit 2xFBn = 0 55 60 65 ms
2xFBn = 1 TLIM = 00 55 60 65
TLIM = 01 15 16 17
TLIM = 10 10 11 12
TLIM = 11 6 6.5 7
SHORT CIRCUIT DETECTION
Vshort ISHORT threshold in 1X mode and during inrush 205 245 mV
Vshort2X ISHORT threshold in 2X mode 280 320
tD_off_SEN Gate turnoff time from SENn input 2xFBn = 0, VDRAINn = 1 V
From VSENn pulsed to 0.425 V.
0.9 µs
2xFBn = 1, VDRAINn = 1 V
From VSENn pulsed to 0.62 V.
0.9
CURRENT FAULT RECOVERY (BACKOFF) TIMING
ted Error delay timing. Delay before next attempt to power a channel following power removal due to error condition PCUT , ILIM or IInrush fault Semi-auto mode 0.8 1 1.2 s
δIfault Duty cycle of Ichannel with current fault 5.5 6.7 %
THERMAL SHUTDOWN
Shutdown temperature Temperature rising 135 146 °C
Hysteresis 7 °C
DIGITAL I/O (SCL, SDAI, A1-A4, /RESET, OSS unless otherwise stated)
VIH Digital input High 2.1 V
VIL Digital input Low 0.9 V
VIT_HYS Input voltage hysteresis 0.17 V
VOL Digital output Low SDAO at 9mA 0.4 V
Digital output Low /INT at 3mA 0.4 V
Rpullup Pullup resistor to VDD /RESET, A1-A4, TEST0 30 50 80
Rpulldown Pulldown resistor to DGND OSS, TEST1, TEST2 30 50 80
tFLT_INT Fault to /INT assertion Time to internally register an Interrupt fault, from Channel turn off 50 500 µs
TRESETmin /RESET input minimum pulse width 5 µs
Tbit_OSS 3-bit OSS bit period MbitPrty = 1 24 25 26 µs
tOSS_IDL Idle time between consecutive shutdown code transmission in 3-bit mode MbitPrty = 1 48 50 µs
tr_OSS Input rise time of OSS in 3-bit mode 0.8 V → 2.3 V, MbitPrty = 1 1 300 ns
tf_OSS Input fall time of OSS in 3-bit mode 2.3 V → 0.8 V, MbitPrty = 1 1 300 ns
I2C TIMING REQUIREMENTS
tPOR Device power-on reset delay 20 ms
fSCL SCL clock frequency 10 400 kHz
tLOW LOW period of the clock 0.5 µs
tHIGH HIGH period of the clock 0.26 µs
tfo SDAO output fall time SDAO, 2.3 V → 0.8 V, Cb = 10 pF, 10 kΩ pull-up to 3.3 V 10 50 ns
SDAO, 2.3 V → 0.8 V, Cb = 400 pF, 1.3 kΩ pull-up to 3.3 V 10 50 ns
CI2C SCL capacitance 10 pF
CI2C_SDA SDAI, SDAO capacitance 6 pF
tSU,DATW Data setup tme (Write operation) 50 ns
tHD,DATW Data hold time (Write operation) 0 ns
tHD,DATR Data hold time (Read operation) 150 400 ns
tfSDA Input fall times of SDAI 2.3 V → 0.8 V 20 120 ns
trSDA Input rise times of SDAI 0.8 V → 2.3 V 20 120 ns
tr Input rise time of SCL 0.8 V → 2.3 V 20 120 ns
tf Input fall time of SCL 2.3 V → 0.8 V 20 120 ns
tBUF Bus free time between a STOP and START condition 0.5 µs
tHD,STA Hold time After (Repeated) START condition 0.26 µs
tSU,STA Repeated START condition setup time 0.26 µs
tSU,STO STOP condition setup time 0.26 µs
tDG Suppressed spike pulse width, SDAI and SCL 50 ns
tWDT_I2C I2C Watchdog trip delay 1.1 2.2 3.3 sec