SLVSF02D March   2019  – May 2020 TPS23881

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Simplified Schematic
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
    1.     Pin Functions
    2. 6.1 Detailed Pin Description
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. Parameter Measurement Information
    1. 8.1 Timing Diagrams
  9. Detailed Description
    1. 9.1 Overview
      1. 9.1.1 Operating Modes
        1. 9.1.1.1 Auto
        2. 9.1.1.2 Semiauto
        3. 9.1.1.3 Manual/Diagnostic
        4. 9.1.1.4 Power Off
      2. 9.1.2 PoE Compliance Terminology
      3. 9.1.3 Channel versus Port Terminology
      4. 9.1.4 Requested Class versus Assigned Class
      5. 9.1.5 Power Allocation and Power Demotion
      6. 9.1.6 Programmable SRAM
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Port Remapping
      2. 9.3.2 Port Power Priority
      3. 9.3.3 Analog-to-Digital Converters (ADC)
      4. 9.3.4 I2C Watchdog
      5. 9.3.5 Current Foldback Protection
    4. 9.4 Device Functional Modes
      1. 9.4.1 Detection
      2. 9.4.2 Connection Check
      3. 9.4.3 Classification
      4. 9.4.4 DC Disconnect
    5. 9.5 I2C Programming
      1. 9.5.1 I2C Serial Interface
    6. 9.6 Register Maps
      1. 9.6.1 Complete Register Set
      2. 9.6.2 Detailed Register Descriptions
        1. 9.6.2.1  INTERRUPT Register
          1. Table 6. INTERRUPT Register Field Descriptions
        2. 9.6.2.2  INTERRUPT MASK Register
          1. Table 7. INTERRUPT MASK Register Field Descriptions
        3. 9.6.2.3  POWER EVENT Register
          1. Table 8. POWER EVENT Register Field Descriptions
        4. 9.6.2.4  DETECTION EVENT Register
          1. Table 9. DETECTION EVENT Register Field Descriptions
        5. 9.6.2.5  FAULT EVENT Register
          1. Table 10. FAULT EVENT Register Field Descriptions
        6. 9.6.2.6  START/ILIM EVENT Register
          1. Table 11. START/ILIM EVENT Register Field Descriptions
        7. 9.6.2.7  SUPPLY and FAULT EVENT Register
          1. Table 12. SUPPLY and FAULT EVENT Register Field Descriptions
          2. 9.6.2.7.1 Detected SRAM Faults and "Safe Mode"
            1. 9.6.2.7.1.1 ULA (Ultra Low Alpha) Package Option: TPS23881A
        8. 9.6.2.8  CHANNEL 1 DISCOVERY Register
        9. 9.6.2.9  CHANNEL 2 DISCOVERY Register
        10. 9.6.2.10 CHANNEL 3 DISCOVERY Register
        11. 9.6.2.11 CHANNEL 4 DISCOVERY Register
          1. Table 13. CHANNEL n DISCOVERY Register Field Descriptions
        12. 9.6.2.12 POWER STATUS Register
          1. Table 14. POWER STATUS Register Field Descriptions
        13. 9.6.2.13 PIN STATUS Register
          1. Table 15. PIN STATUS Register Field Descriptions
        14. 9.6.2.14 OPERATING MODE Register
          1. Table 16. OPERATING MODE Register Field Descriptions
        15. 9.6.2.15 DISCONNECT ENABLE Register
          1. Table 20. DISCONNECT ENABLE Register Field Descriptions
        16. 9.6.2.16 DETECT/CLASS ENABLE Register
          1. Table 21. DETECT/CLASS ENABLE Register Field Descriptions
        17. 9.6.2.17 Power Priority / 2Pair PCUT Disable Register Name
          1. Table 22. Power Priority / 2P-PCUT Disable Register Field Descriptions
        18. 9.6.2.18 TIMING CONFIGURATION Register
          1. Table 24. TIMING CONFIGURATION Register Field Descriptions
        19. 9.6.2.19 GENERAL MASK Register
          1. Table 25. GENERAL MASK Register Field Descriptions
        20. 9.6.2.20 DETECT/CLASS RESTART Register
          1. Table 27. DETECT/CLASS RESTART Register Field Descriptions
        21. 9.6.2.21 POWER ENABLE Register
          1. Table 28. POWER ENABLE Register Field Descriptions
        22. 9.6.2.22 RESET Register
          1. Table 32. RESET Register Field Descriptions
        23. 9.6.2.23 ID Register
          1. Table 34. ID Register Field Descriptions
        24. 9.6.2.24 Connection Check and Auto Class Status Register
          1. Table 35. Connection Check and Auto Class Field Descriptions
        25. 9.6.2.25 2-Pair Police Ch-1 Configuration Register
        26. 9.6.2.26 2-Pair Police Ch-2 Configuration Register
        27. 9.6.2.27 2-Pair Police Ch-3 Configuration Register
        28. 9.6.2.28 2-Pair Police Ch-4 Configuration Register
          1. Table 36. 2-Pair Policing Register Fields Descriptions
        29. 9.6.2.29 Capacitance (Legacy PD) Detection
          1. Table 39. Capacitance Detection Register Field Descriptions
        30. 9.6.2.30 Power-on Fault Register
          1. Table 40. Power-on Fault Register Field Descriptions
        31. 9.6.2.31 PORT RE-MAPPING Register
          1. Table 41. PORT RE-MAPPING Register Field Descriptions
        32. 9.6.2.32 Channels 1 and 2 Multi Bit Priority Register
        33. 9.6.2.33 Channels 3 and 4 Multi Bit Priority Register
          1. Table 42. Channels n MBP Register Field Descriptions
        34. 9.6.2.34 4-Pair Wired and Port Power Allocation Register
          1. Table 44. 4-Pair Wired and Power Allocation Register Field Descriptions
        35. 9.6.2.35 4-Pair Police Ch-1 and 2 Configuration Register
        36. 9.6.2.36 4-Pair Police Ch-3 and 4 Configuration Register
          1. Table 46. 4-Pair Police Register Field Descriptions
        37. 9.6.2.37 TEMPERATURE Register
          1. Table 48. TEMPERATURE Register Field Descriptions
        38. 9.6.2.38 4-Pair Fault Configuration Register
          1. Table 49. 4-Pair Fault Register Field Descriptions
        39. 9.6.2.39 INPUT VOLTAGE Register
          1. Table 50. INPUT VOLTAGE Register Field Descriptions
        40. 9.6.2.40 CHANNEL 1 CURRENT Register
        41. 9.6.2.41 CHANNEL 2 CURRENT Register
        42. 9.6.2.42 CHANNEL 3 CURRENT Register
        43. 9.6.2.43 CHANNEL 4 CURRENT Register
          1. Table 51. CHANNEL n CURRENT Register Field Descriptions
        44. 9.6.2.44 CHANNEL 1 VOLTAGE Register
        45. 9.6.2.45 CHANNEL 2 VOLTAGE Register
        46. 9.6.2.46 CHANNEL 3 VOLTAGE Register
        47. 9.6.2.47 CHANNEL 4 VOLTAGE Register
          1. Table 52. CHANNEL n VOLTAGE Register Field Descriptions
        48. 9.6.2.48 2x FOLDBACK SELECTION Register
          1. Table 53. 2x FOLDBACK SELECTION Register Field Descriptions
        49. 9.6.2.49 FIRMWARE REVISION Register
          1. Table 54. FIRMWARE REVISION Register Field Descriptions
        50. 9.6.2.50 I2C WATCHDOG Register
          1. Table 55. I2C WATCHDOG Register Field Descriptions
        51. 9.6.2.51 DEVICE ID Register
          1. Table 57. DEVICE ID Register Field Descriptions
        52. 9.6.2.52 CHANNEL 1 DETECT RESISTANCE Register
        53. 9.6.2.53 CHANNEL 2 DETECT RESISTANCE Register
        54. 9.6.2.54 CHANNEL 3 DETECT RESISTANCE Register
        55. 9.6.2.55 CHANNEL 4 DETECT RESISTANCE Register
          1. Table 58. DETECT RESISTANCE Register Fields Descriptions
        56. 9.6.2.56 CHANNEL 1 DETECT CAPACITANCE Register
        57. 9.6.2.57 CHANNEL 2 DETECT CAPACITANCE Register
        58. 9.6.2.58 CHANNEL 3 DETECT CAPACITANCE Register
        59. 9.6.2.59 CHANNEL 4 DETECT CAPACITANCE Register
          1. Table 59. DETECT CAPACITANCE Register Fields Descriptions
        60. 9.6.2.60 CHANNEL 1 ASSIGNED CLASS Register
        61. 9.6.2.61 CHANNEL 2 ASSIGNED CLASS Register
        62. 9.6.2.62 CHANNEL 3 ASSIGNED CLASS Register
        63. 9.6.2.63 CHANNEL 4 ASSIGNED CLASS Register
          1. Table 60. CHANNEL n ASSIGNED CLASS Register Field Descriptions
        64. 9.6.2.64 AUTO CLASS CONTROL Register
          1. Table 63. AUTO CLASS CONTROL Register Field Descriptions
        65. 9.6.2.65 CHANNEL 1 AUTO CLASS POWER Register
        66. 9.6.2.66 CHANNEL 2 AUTO CLASS POWER Register
        67. 9.6.2.67 CHANNEL 3 AUTO CLASS POWER Register
        68. 9.6.2.68 CHANNEL 4 AUTO CLASS POWER Register
          1. Table 65. AUTO CLASS POWER Register Fields Descriptions
        69. 9.6.2.69 ALTERNATIVE FOLDBACK Register
          1. Table 66. ALTERNATIVE FOLDBACK Register Field Descriptions
        70. 9.6.2.70 SRAM CONTROL Register
          1. Table 67.  SRAM CONTROL Register Field Descriptions
          2. 9.6.2.70.1 SRAM START ADDRESS (LSB) Register
          3. 9.6.2.70.2 SRAM START ADDRESS (MSB) Register
            1. Table 68. SRAM START ADDRESS Register Field Descriptions
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Introduction to PoE
        1. 10.1.1.1 2-Pair Versus 4-Pair Power and the New IEEE802.3bt Standard
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Connections on Unused Channels
        2. 10.2.2.2 Power Pin Bypass Capacitors
        3. 10.2.2.3 Per Port Components
        4. 10.2.2.4 System Level Components (not shown in the schematic diagrams)
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
    1. 11.1 VDD
    2. 11.2 VPWR
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Kelvin Current Sensing Resistors
    2. 12.2 Layout Example
      1. 12.2.1 Component Placement and Routing Guidelines
        1. 12.2.1.1 Power Pin Bypass Capacitors
        2. 12.2.1.2 Per-Port Components
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Support Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

GENERAL MASK Register

COMMAND = 17h with 1 Data Byte, Read/Write

Figure 63. GENERAL MASK Register Format
7 6 5 4 3 2 1 0
INTEN nbitACC MbitPrty CLCHE DECHE
R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 25. GENERAL MASK Register Field Descriptions

Bit Field Type Reset Description
7 INTEN R/W 1 INT pin mask bit. Writing a 0 will mask any bit of Interrupt register from activating the INT output, whatever the state of the Interrupt Mask register. Note that activating INTEN has no impact on the event registers.

1 = Any unmasked bit of Interrupt register can activate the INT output

0 = INT output cannot be activated

6 R/W 0
5 nbitACC R/W 0 I2C Register Access Configuration bit.

1 = Configuration B. This means 16-bit access with a single device address (A0 = 0).

0 = Configuration A. This means 8-bit access, while the 8-channel device is treated as 2 separate 4-channel devices with 2 consecutive slave addresses.

See register 0x11 for more information on the I2C address programming

4 MbitPrty R/W 0 Multi Bit Priority bit. Used to select between 1-bit shutdown priority and 3-bit shutdown priority.

1 = 3-bit shutdown priority. Register 0x27 and 0x28 need to be followed for priority and OSS action.

0 = 1-bit shutdown priority. Register 0x15 needs to be followed for priority and OSS action

3 CLCHE R/W 0 Class change Enable bit. When set, the CLSCn bits in Detection Event register only indicates when the result of the most current classification operation differs from the result of the previous one.

1 = CLSCn bit is set only when a change of class occurred for the associated channel.

0 = CLSCn bit is set each time a classification cycle occurred for the associated channel.

2 DECHE R/W 0 Detect Change Enable bit. When set, the DETCn bits in Detection Event register only indicates when the result of the most current detection operation differs from the result of the previous one.

1 = DETCn bit is set only when a change in detection occurred for the associated channel.

0 = DETCn bit is set each time a detection cycle occurred for the associated channel.

1 R/W 0
0 R/W 0

SPACE

NOTE

If the MbitPrty bit needs to be changed from 0 to 1, make sure the OSS input pin is in the idle (low) state for a minimum of 200 µsec prior to setting the MbitPrty bit, to avoid any misbehavior related to loss of synchronization with the OSS bit stream.

NOTE

Only the nbitACC bit for channels 1-4 needs to be set to enable 16-bit I2C operation.

Table 26. nbitACC = 1: Register Operations in 8-Bit (Config A) and 16-bit (Config B) I2C Mode

Cmd Code Register or Command Name Bits Description Configuration A (8-bit) Configuration B (16-bit)
00h INTERRUPT INT bits P1-4, P5-8 Separate mask and interrupt result per group of 4 channels.
The Supply event bit is repeated twice.
01h INTERRUPT MASK MSK bits P1-4, P5-8
02h POWER EVENT PGC_PEC P4-1, P8-5 Separate event byte per group of 4 channels.
03h
04h DETECTION EVENT CLS_DET P4-1, P8-5
05h
06h FAULT EVENT DIS_PCUT P4-1, P8-5
07h
08h START/ILIM EVENT ILIM_STR P4-1, P8-5
09h
0Ah SUPPLY/FAULT EVENT TSD, VDUV, VDUW, VPUV , RAMFLT PCUT34, PCUT12, PCUT78, PCUT56, OSSE4-1, OSSE8-5 Both 8-bit registers (channel 1 to 4 and channel 5 to 8) will show the same results for TSD, VDUV, VPUV and RAMFLT. The PCUTxx and OSSEx bits will. have separate status per group of 4 channels.
Clearing at least one VPUV/VDUV also clears the other one.
0Bh
0Ch CHANNEL 1 DISCOVERY CLS&DET1_CLS&DET5 Separate Status byte per channel
0Dh CHANNEL 2 DISCOVERY CLS&DET2_CLS&DET6
0Eh CHANNEL 3 DISCOVERY CLS&DET3_CLS&DET7
0Fh CHANNEL 4 DISCOVERY CLS&DET4_CLS&DET8
10h POWER STATUS PG_PE P4-1, P8-5 Separate status byte per group of 4 channels
11h PIN STATUS A4-A1,A0 Both 8-bit registers (channel 1 to 4 and channel 5 to 8) will show the same result, except that A0 = 0 (channel 1 to 4) or 1 (channel 5 to 8). Both 8-bit registers (channel 1 to 4 and channel 5 to 8) will show the same result, including A0 = 0.
12h OPERATING MODE MODE P4-1, P8-5 Separate Mode byte per group of 4 channels.
13h DISCONNECT ENABLE DCDE P4-1, P8-5 Separate DC disconnect enable byte per group of 4 channels.
14h DETECT/CLASS ENABLE CLE_DETE P4-1, P8-5 Separate Detect/Class Enable byte per group of 4 channels.
15h PWRPR/2P-PCUT DISABLE OSS_DCUT P4-1, P8-5 Separate OSS/DCUT byte per group of 4 channels.
16h TIMING CONFIG TLIM_TSTRT_TOVLD_TMPDO P4-1,
P8-5
Separate Timing byte per group of 4 channels.
17h GENERAL MASK P4-1, P8-5 including n-bit access Separate byte per group of 4 channels.
n-bit access: Setting this in at least one of the virtual quad register space is enough to enter Config B mode. To go back to config A, clear both.
MbitPrty: Setting this in at least one of the virtual quad register space is enough to enter 3-bit shutdown priority. To go back to 1-bit shutdown, clear both MbitPrty bits.
18h DETECT/CLASS Restart RCL_RDET P4-1, P8-5 Separate DET/CL RST byte per group of 4 channels
19h POWER ENABLE POF_PWON P4-1, P8-5 Separate POF/PWON byte per group of 4 channels
1Ah RESET P4-1, P8-5 Separate byte per group of 4 channels, Clear Int pin and Clear All int.
Separate byte per group of 4 channels.
1Bh ID Both 8-bit registers (channel 1 to 4 and channel 5 to 8) will show the same result unless modified through I2C.
1Ch Autoclass and Connecttion Chech AC4-1, CC34 - 12, AC8-5, CC78-56 Separate byte per group of 4 channels.
1Eh 2P POLICE 1/5 CONFIG POL1, POL5 Separate Policing byte per channel.
1Fh 2P POLICE 2/6 CONFIG POL2, POL6
20h 2P POLICE 3/7 CONFIG POL3, POL7
21h 2P POLICE 4/8 CONFIG POL4, POL8
22h CAP MEASUREMENT CDET4-1, CDET8-5 Separate capacitance measurement enable bytes per group of 4 channels.
24h Power-on FAULT PF P4-1, P8-5 Separate Power-on FAULT byte per group of 4 channels
25h
26h PORT REMAPPING Logical P4-1, P8-5 Separate Remapping byte per group of 4 channels.
Reinitialized only if POR or RESET pin. Kept unchanged if 0x1A IC reset or CPU watchdog reset.
27h Multi-Bit Priority 21 / 65 MBP2-1, MBP6-5 Separate MBP byte per group of 2 channels
28h Multi-Bit Priority 43 / 87 MBP4-3, MBP8-7 Separate MBP byte per group of 2 channels
29h PORT POWER ALLOCATION 4PW34-12, MC34-12, 4PW78-56, MC78-56 Separate 4Pnn, MCnn byte per group of 4 channels
2Ah 4P POLICE 12 / 56 CONFIG POL12, POL56 Separate 4P Policing byte per channel
2Bh 4P POLICE 34 / 78CONFIG POL34, POL78 Separate 4P Policing byte per channel
2Ch TEMPERATURE TEMP P1-4, P5-8 Both 8-bit registers (channel 1 to 4 and channel 5 to 8) must show the same result.
2Dh 4P FAULT CONFIG NLM4-1, NCT4-1, 4PPCT4-1,DCDT4-1, NLM8-5, NCT8-5, 4PPCT8-5,DCDT8-5 Separate fault handling byte per group of 4 channels
2Eh INPUT VOLTAGE VPWR P1-4, P5-8 Both 8-bit registers (channel 1 to 4 and channel 5 to 8) must show the same result.
2Fh
30h CHANNEL 1 CURRENT I1, I5 Separate 2-byte per group of 4 channels Separate 2-byte per group of 4 channels.
2-byte Read at 0x30 gives I1
4-byte Read at 0x30 gives I1, I5.
31h N/A 2-byte Read at 0x31 gives I5.
32h CHANNEL 1 VOLTAGE V1, V5 Separate 2-byte per group of 4 channels 2-byte Read at 0x32 gives V1
4-byte Read at 0x32 gives V1, V5.
33h N/A 2-byte Read at 0x33 gives V5.
34h CHANNEL 2 CURRENT I2, I6 Separate 2-byte per group of 4 channels 2-byte Read at 0x34 gives I2
4-byte Read at 0x34 gives I2, I6.
35h N/A 2-byte Read at 0x35 gives I6.
36h CHANNEL 2 VOLTAGE V2, V6 Separate 2-byte per group of 4 channels 2-byte Read at 0x36 gives V2
4-byte Read at 0x36 gives V2, V6.
37h N/A 2-byte Read at 0x37 gives V6.
38h CHANNEL 3 CURRENT I3, I7 Separate 2-byte per group of 4 channels 2-byte Read at 0x38 gives I3
4-byte Read at 0x38 gives I3, I7.
39h N/A 2-byte Read at 0x39 gives I7.
3Ah CHANNEL 3 VOLTAGE V3, V7 Separate 2-byte per group of 4 channels 2-byte Read at 0x3A gives V3
4-byte Read at 0x3A gives V3, V7.
3Bh N/A 2-byte Read at 0x3B gives V7.
3Ch CHANNEL 4 CURRENT I4, I8 Separate 2-byte per group of 4 channels 2-byte Read at 0x3C gives I4
4-byte Read at 0x3C gives I4, I8.
3Dh N/A 2-byte Read at 0x3D gives I8.
3Eh CHANNEL 4 VOLTAGE V4, V8 Separate 2-byte per group of 4 channels 2-byte Read at 0x3E gives V4
4-byte Read at 0x3E gives V4, V8.
3Fh N/A 2-byte Read at 0x3F gives V8.
40h OPERATIONAL FOLDBACK 2xFB4-1, 2xFB8-5 Separate 2xFBn config byte per group of 4 channels.
41h FIRMWARE REVISION FRV P1-4, P5-8 Both 8-bit registers (channel 1 to 4 and channel 5 to 8) must show the same result.
42h I2C WATCHDOG P1-4, P5-8 IWD3-0: if at least one of the two 4-port settings is different than 1011b, the watchdog is enabled for all 8 channels.
WDS: Both 8-bit registers (channel 1 to 4 and channel 5 to 8) must show the same WDS result. Each WDS bit needs to be cleared individually through I2C.
43h DEVICE ID DID_SR P1-4, P5-8 Both 8-bit registers (channel 1 to 4 and channel 5 to 8) will show the same result .
44h CHANNEL 1 RESISTANCE RDET1, RDET5 Separate byte per channel.
Detection resistance always updated, detection good or bad.
45h CHANNEL 2 RESISTANCE RDET2, RDET6
46h CHANNEL 3 RESISTANCE RDET3, RDET7
47h CHANNEL 4 RESISTANCE RDET4, RDET8
4Ch CHANNEL 1 ASSIGNED CLASS ACLS&PCLS1_ACLS&PCLS5 Separate Status byte per channel
4Dh CHANNEL 2 ASSIGNED CLASS ACLS&PCLS2_ACLS&PCLS6
4Eh CHANNEL 3 ASSIGNED CLASS ACLS&PCLS3_ACLS&PCLS7
4Fh CHANNEL 4 ASSIGNED CLASS ACLS&PCLS4_ACLS&PCLS8
50h AUTOCLASS CONTROL MAC4-1, AAC4-1, MAC8-5, AAC8-5 Separate Auto Class control bytes per 4 channels
51h AUTOCLASS POWER 1/5 PAC1, PAC5 Separate Auto Class Power Measurement byte per channel
52h AUTOCLASS POWER 2/6 PAC2, PAC6
53h AUTOCLASS POWER 3/7 PAC3, PAC7
54h AUTOCLASS POWER 4/8 PAC4, PAC8
55h ALTERNATIVE FOLDBACK ALTFB4-1, ALTIR4-1, ALTFN8-5, ALTIR8-5 Separate Alternative Foldback byte per group of 4 channels
60h SRAM CONTROL SRAM CNTRL BITS These bits must be configured for the lower virtual quad (A0=0, CH 1-4)). These bits have no functionality for the upper virtual quad (A0=1, Ch 5-8) device
61h SRAM DATA Streaming data input is independent of I2C configuration
62h START ADDRESS (LSB) These bits must be configured for the lower virtual quad (A0=0, CH 1-4)). These bits have no functionality for the upper virtual quad (A0=1, Ch 5-8) device
63h START ADDRESS (MSB) These bits must be configured for the lower virtual quad (A0=0, CH 1-4)). These bits have no functionality for the upper virtual quad (A0=1, Ch 5-8) device