SLVSF02D March 2019 – May 2020 TPS23881
COMMAND = 42h with 1 Data Byte, Read/Write
The I2C watchdog timer monitors the I2C clock line in order to prevent hung software situations that could leave ports in a hazardous state. The timer can be reset by either edge on SCL input. If the watchdog timer expires, all channels will be turned off and WDS bit will be set. The nominal watchdog time-out period is 2 seconds.
|LEGEND: R/W = Read/Write; R = Read only; -n = value after reset|
I2C Watchdog disable. When equal to 1011b, the watchdog is masked. Otherwise, it is umasked and the watchdog is operational.
|0||WDS||R/W||0||I2C Watchdog timer status, valid even if the watchdog is masked. When set, it means that the watchdog timer has expired without any activity on I2C clock line. Writing 0 at WDS location clears it.
Note that when the watchdog timer expires and if the watchdog is unmasked, all channels are also turned off.
When the channels are turned OFF due to I2C watchdog, the corresponding bits are also cleared:
|Register||Bits to be Reset|
|0x04||CLSCn and DETCn|
|0x06||DISFn and PCUTn|
|0x08||STRTn and ILIMn|
|0x0C-0F||Requested Class and Detection|
|0x10||PGn and PEn|
|0x14||CLEn and DETEn|
|0x1C||ACn and CCnn|
|0x1E-21||2P Policing set to 0xFFh|
|0x2A-2B||4P Policing set to 0xFFh|
|0x2D||NLMnn, NCTnn, 4PPCTnn, and DCDTnn|
|0x30-3F||Channel Voltage and Current Measurements|
|0x44 - 47||Detection Resistance Measurements|
|0x4C-4F||Assigned Class and Previous Class|
The corresponding PGCn and PECn bits of Power Event register will also be set if there is a change. The corresponding PEn and PGn bits of Power Status Register are also updated accordingly.
If the I2C watchdog timer has expired, the Temperature and Input voltage registers will stop being updated until the WDS bit is cleared. The WDS bit must then be cleared to allow these registers to work normally.