SLVSF02D March 2019 – May 2020 TPS23881
An I2C Watchdog timer is available on the TPS23881 device. The timer monitors the I2C, SCL line for clock edges. When enabled, a timeout of the watchdog resets the I2C interface along with any active ports. This feature provides protection in the event of a hung software situation or I2C bus hang-up by slave devices. In the latter case, if a slave is attempting to send a data bit of 0 when the master stops sending clocks, then the slave my drive the data line low indefinitely. Because the data line is driven low, the master cannot send a STOP to clean up the bus. Activating the I2C watchdog feature of the TPS23881 clears this deadlocked condition. If the timer of two seconds expires, the ports latch off and the WD status bit is set. Note that WD Status will be set even if the watchdog is not enabled. The WD status bit may only be cleared by a device reset or writing a 0 to the WDS status bit location. The 4-bit watchdog disable field shuts down this feature when a code of 1011b is loaded. This field is preset to 1011b whenever the TPS23881 is initially powered. See I2C WATCHDOG Register for more details.