SLVSF02D March 2019 – May 2020 TPS23881
COMMAND = 60h with 1 Data Byte, Read/Write
|LEGEND: R/W = Read/Write; R = Read only; -n = value after reset|
|7||PROG_SEL||R/W||0||I2C Programming select bit.
1 = SRAM I2C read/write is enabled
0 = SRAM I2C read/write is disabled.
|6||CPU_RST||R/W||0||CPU Reset bit
1 = Internal CPU is held in RESET
0 = Internal CPU is active
This is strictly a CPU reset. Toggling this bit reset the cpu only and will not change any contents of the I2C registers
|4||PAR_EN||R/W||0|| SRAM Parity Enable bit:
1 = SRAM Parity Check will be enabled
0 = SRAM Parity Check will be disabled
It is recommended that the Parity function be enable whenever SRAM is being used
|3||RAM_EN||R/W||0||SRAM Enable bit
1 = SRAM will be enabled and the internal CPU will run from both SRAM and internal ROM
0 = Internal CPU will run from internal ROM only
This bit needs to be set to a 1 after SRAM programing to enable the utilization of the SRAM code
|2||PAR_SEL||R/W||0||SRAM Parity Select bit: Setting this bit to a 1 in conjunction with the RZ/W bit enables access to the SRAM Parity bits.
1 = Parity bits read/write is enabled
0 = Parity bits read/write is disabled
|1||R/WZ||R/W||0||SRAM Read/Write select bit:
0 = SRAM Write – SRAM data is written with a write to 0x61h
1 = SRAM Read – SRAM data is read with a read from 0x61h
SRAM data can be continuously read/written over I2C until a STOP bit is sent.
|0||CLR_PTR||R/W||0||Clear Address Pointer bit:
1 = Resets the memory address pointer
0 = Releases pointer for use
In order to ensure proper programming, this bit should be toggled (0-1-0) to writing or reading the SRAM or Parity memory.