SLVSF02D March   2019  – May 2020 TPS23881

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Simplified Schematic
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
    1.     Pin Functions
    2. 6.1 Detailed Pin Description
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. Parameter Measurement Information
    1. 8.1 Timing Diagrams
  9. Detailed Description
    1. 9.1 Overview
      1. 9.1.1 Operating Modes
        1. 9.1.1.1 Auto
        2. 9.1.1.2 Semiauto
        3. 9.1.1.3 Manual/Diagnostic
        4. 9.1.1.4 Power Off
      2. 9.1.2 PoE Compliance Terminology
      3. 9.1.3 Channel versus Port Terminology
      4. 9.1.4 Requested Class versus Assigned Class
      5. 9.1.5 Power Allocation and Power Demotion
      6. 9.1.6 Programmable SRAM
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Port Remapping
      2. 9.3.2 Port Power Priority
      3. 9.3.3 Analog-to-Digital Converters (ADC)
      4. 9.3.4 I2C Watchdog
      5. 9.3.5 Current Foldback Protection
    4. 9.4 Device Functional Modes
      1. 9.4.1 Detection
      2. 9.4.2 Connection Check
      3. 9.4.3 Classification
      4. 9.4.4 DC Disconnect
    5. 9.5 I2C Programming
      1. 9.5.1 I2C Serial Interface
    6. 9.6 Register Maps
      1. 9.6.1 Complete Register Set
      2. 9.6.2 Detailed Register Descriptions
        1. 9.6.2.1  INTERRUPT Register
          1. Table 6. INTERRUPT Register Field Descriptions
        2. 9.6.2.2  INTERRUPT MASK Register
          1. Table 7. INTERRUPT MASK Register Field Descriptions
        3. 9.6.2.3  POWER EVENT Register
          1. Table 8. POWER EVENT Register Field Descriptions
        4. 9.6.2.4  DETECTION EVENT Register
          1. Table 9. DETECTION EVENT Register Field Descriptions
        5. 9.6.2.5  FAULT EVENT Register
          1. Table 10. FAULT EVENT Register Field Descriptions
        6. 9.6.2.6  START/ILIM EVENT Register
          1. Table 11. START/ILIM EVENT Register Field Descriptions
        7. 9.6.2.7  SUPPLY and FAULT EVENT Register
          1. Table 12. SUPPLY and FAULT EVENT Register Field Descriptions
          2. 9.6.2.7.1 Detected SRAM Faults and "Safe Mode"
            1. 9.6.2.7.1.1 ULA (Ultra Low Alpha) Package Option: TPS23881A
        8. 9.6.2.8  CHANNEL 1 DISCOVERY Register
        9. 9.6.2.9  CHANNEL 2 DISCOVERY Register
        10. 9.6.2.10 CHANNEL 3 DISCOVERY Register
        11. 9.6.2.11 CHANNEL 4 DISCOVERY Register
          1. Table 13. CHANNEL n DISCOVERY Register Field Descriptions
        12. 9.6.2.12 POWER STATUS Register
          1. Table 14. POWER STATUS Register Field Descriptions
        13. 9.6.2.13 PIN STATUS Register
          1. Table 15. PIN STATUS Register Field Descriptions
        14. 9.6.2.14 OPERATING MODE Register
          1. Table 16. OPERATING MODE Register Field Descriptions
        15. 9.6.2.15 DISCONNECT ENABLE Register
          1. Table 20. DISCONNECT ENABLE Register Field Descriptions
        16. 9.6.2.16 DETECT/CLASS ENABLE Register
          1. Table 21. DETECT/CLASS ENABLE Register Field Descriptions
        17. 9.6.2.17 Power Priority / 2Pair PCUT Disable Register Name
          1. Table 22. Power Priority / 2P-PCUT Disable Register Field Descriptions
        18. 9.6.2.18 TIMING CONFIGURATION Register
          1. Table 24. TIMING CONFIGURATION Register Field Descriptions
        19. 9.6.2.19 GENERAL MASK Register
          1. Table 25. GENERAL MASK Register Field Descriptions
        20. 9.6.2.20 DETECT/CLASS RESTART Register
          1. Table 27. DETECT/CLASS RESTART Register Field Descriptions
        21. 9.6.2.21 POWER ENABLE Register
          1. Table 28. POWER ENABLE Register Field Descriptions
        22. 9.6.2.22 RESET Register
          1. Table 32. RESET Register Field Descriptions
        23. 9.6.2.23 ID Register
          1. Table 34. ID Register Field Descriptions
        24. 9.6.2.24 Connection Check and Auto Class Status Register
          1. Table 35. Connection Check and Auto Class Field Descriptions
        25. 9.6.2.25 2-Pair Police Ch-1 Configuration Register
        26. 9.6.2.26 2-Pair Police Ch-2 Configuration Register
        27. 9.6.2.27 2-Pair Police Ch-3 Configuration Register
        28. 9.6.2.28 2-Pair Police Ch-4 Configuration Register
          1. Table 36. 2-Pair Policing Register Fields Descriptions
        29. 9.6.2.29 Capacitance (Legacy PD) Detection
          1. Table 39. Capacitance Detection Register Field Descriptions
        30. 9.6.2.30 Power-on Fault Register
          1. Table 40. Power-on Fault Register Field Descriptions
        31. 9.6.2.31 PORT RE-MAPPING Register
          1. Table 41. PORT RE-MAPPING Register Field Descriptions
        32. 9.6.2.32 Channels 1 and 2 Multi Bit Priority Register
        33. 9.6.2.33 Channels 3 and 4 Multi Bit Priority Register
          1. Table 42. Channels n MBP Register Field Descriptions
        34. 9.6.2.34 4-Pair Wired and Port Power Allocation Register
          1. Table 44. 4-Pair Wired and Power Allocation Register Field Descriptions
        35. 9.6.2.35 4-Pair Police Ch-1 and 2 Configuration Register
        36. 9.6.2.36 4-Pair Police Ch-3 and 4 Configuration Register
          1. Table 46. 4-Pair Police Register Field Descriptions
        37. 9.6.2.37 TEMPERATURE Register
          1. Table 48. TEMPERATURE Register Field Descriptions
        38. 9.6.2.38 4-Pair Fault Configuration Register
          1. Table 49. 4-Pair Fault Register Field Descriptions
        39. 9.6.2.39 INPUT VOLTAGE Register
          1. Table 50. INPUT VOLTAGE Register Field Descriptions
        40. 9.6.2.40 CHANNEL 1 CURRENT Register
        41. 9.6.2.41 CHANNEL 2 CURRENT Register
        42. 9.6.2.42 CHANNEL 3 CURRENT Register
        43. 9.6.2.43 CHANNEL 4 CURRENT Register
          1. Table 51. CHANNEL n CURRENT Register Field Descriptions
        44. 9.6.2.44 CHANNEL 1 VOLTAGE Register
        45. 9.6.2.45 CHANNEL 2 VOLTAGE Register
        46. 9.6.2.46 CHANNEL 3 VOLTAGE Register
        47. 9.6.2.47 CHANNEL 4 VOLTAGE Register
          1. Table 52. CHANNEL n VOLTAGE Register Field Descriptions
        48. 9.6.2.48 2x FOLDBACK SELECTION Register
          1. Table 53. 2x FOLDBACK SELECTION Register Field Descriptions
        49. 9.6.2.49 FIRMWARE REVISION Register
          1. Table 54. FIRMWARE REVISION Register Field Descriptions
        50. 9.6.2.50 I2C WATCHDOG Register
          1. Table 55. I2C WATCHDOG Register Field Descriptions
        51. 9.6.2.51 DEVICE ID Register
          1. Table 57. DEVICE ID Register Field Descriptions
        52. 9.6.2.52 CHANNEL 1 DETECT RESISTANCE Register
        53. 9.6.2.53 CHANNEL 2 DETECT RESISTANCE Register
        54. 9.6.2.54 CHANNEL 3 DETECT RESISTANCE Register
        55. 9.6.2.55 CHANNEL 4 DETECT RESISTANCE Register
          1. Table 58. DETECT RESISTANCE Register Fields Descriptions
        56. 9.6.2.56 CHANNEL 1 DETECT CAPACITANCE Register
        57. 9.6.2.57 CHANNEL 2 DETECT CAPACITANCE Register
        58. 9.6.2.58 CHANNEL 3 DETECT CAPACITANCE Register
        59. 9.6.2.59 CHANNEL 4 DETECT CAPACITANCE Register
          1. Table 59. DETECT CAPACITANCE Register Fields Descriptions
        60. 9.6.2.60 CHANNEL 1 ASSIGNED CLASS Register
        61. 9.6.2.61 CHANNEL 2 ASSIGNED CLASS Register
        62. 9.6.2.62 CHANNEL 3 ASSIGNED CLASS Register
        63. 9.6.2.63 CHANNEL 4 ASSIGNED CLASS Register
          1. Table 60. CHANNEL n ASSIGNED CLASS Register Field Descriptions
        64. 9.6.2.64 AUTO CLASS CONTROL Register
          1. Table 63. AUTO CLASS CONTROL Register Field Descriptions
        65. 9.6.2.65 CHANNEL 1 AUTO CLASS POWER Register
        66. 9.6.2.66 CHANNEL 2 AUTO CLASS POWER Register
        67. 9.6.2.67 CHANNEL 3 AUTO CLASS POWER Register
        68. 9.6.2.68 CHANNEL 4 AUTO CLASS POWER Register
          1. Table 65. AUTO CLASS POWER Register Fields Descriptions
        69. 9.6.2.69 ALTERNATIVE FOLDBACK Register
          1. Table 66. ALTERNATIVE FOLDBACK Register Field Descriptions
        70. 9.6.2.70 SRAM CONTROL Register
          1. Table 67.  SRAM CONTROL Register Field Descriptions
          2. 9.6.2.70.1 SRAM START ADDRESS (LSB) Register
          3. 9.6.2.70.2 SRAM START ADDRESS (MSB) Register
            1. Table 68. SRAM START ADDRESS Register Field Descriptions
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Introduction to PoE
        1. 10.1.1.1 2-Pair Versus 4-Pair Power and the New IEEE802.3bt Standard
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Connections on Unused Channels
        2. 10.2.2.2 Power Pin Bypass Capacitors
        3. 10.2.2.3 Per Port Components
        4. 10.2.2.4 System Level Components (not shown in the schematic diagrams)
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
    1. 11.1 VDD
    2. 11.2 VPWR
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Kelvin Current Sensing Resistors
    2. 12.2 Layout Example
      1. 12.2.1 Component Placement and Routing Guidelines
        1. 12.2.1.1 Power Pin Bypass Capacitors
        2. 12.2.1.2 Per-Port Components
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Support Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

SRAM START ADDRESS (MSB) Register

COMMAND = 63h with 1 Byte, Read/Write

Figure 121. SRAM START ADDRESS (MSB) Register Format
7 6 5 4 3 2 1 0
SA_15 SA_14 SA_13 SA_12 SA_11 SA_10 SA_9 SA_8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 68. SRAM START ADDRESS Register Field Descriptions

Bit Field Type Reset Description
15-0 SA_15- SA_0 R/W 0 SRAM and Parity Programing Start Address bits:

the value entered into these registers sets the start address location for the SRAM or Parity programming

SRAM Programming:

Upon power up, it is recommended that the TPS23881 device's SRAM be programmed with the latest version of SRAM code via the I2C to ensure proper operation and IEEE complaint performance. All I2C traffic other than those commands required to program the SRAM should be deferred until after the SRAM programming sequences are completed.

NOTE

The latest version of firmware and SRAM release notes may be accessed from the TI mySecure Software webpage.

The SRAM Release Notes and ROM Advisory document includes more detailed information regarding any know issues and changes that were associated with each firmware release.

NOTE

The SRAM programming control must be completed at the lower I2C address (Channels 1-4, A0 = 0). Configuring this registers for the upper I2C device address (Channels 5-8) will not program the SRAM

For systems that include multiple TPS23881 devices, the 0x7F "global" broadcast I2C address may be used to programmed all of the devices at the same time.

NOTE

The SRAM programming needs to be delayed at least 50ms from the initial power on (VPWR and VDD above UVLO) of the device to allow for the device to complete its internal hardware initialization process

NOTE

For more detailed instructions on the SRAM programing procedures please refer the How to Load TPS2388x SRAM Code document on TI.com.

SPACE

0x60h setup for SRAM Programming: Prior to programming/writing the SRAM, the following bits sequence needs to be completed in register 0x60h:

7 6 5 4 3 2 1 0
PROG_SEL CPU_RST - PAR_EN RAM_EN PAR_SEL R/WZ CLR_PTR
0 → 1 0 → 1 0 0 0 0 1 → 0 0 → 1 → 0

The same sequence is required to read the SRAM with the exception that the R/WZ bit needs to be set to “1”.

If the device is in “Safe Mode”, the same sequence as above may be used to reprogram the SRAM.

An I2C write to 0x61h following this sequence actively programs the SRAM program memory starting from the address set in registers 0x62h and 63h.

0x60h setup for SRAM Parity Programming: Following the programming of the SRAM program memory, the following bits sequence needs to be completed in register 0x60h in order to configure the device to program the Parity memory:

7 6 5 4 3 2 1 0
PROG_SEL CPU_RST - PAR_EN RAM_EN PAR_SEL R/WZ CLR_PTR
0 → 1 0 → 1 0 0 0 0 → 1 1 → 0 0 → 1 → 0

The same sequence is required to read the Parity with the exception that the R/WZ bit needs to be set to “1".

An I2C write to 0x61h following this sequence actively programs the Parity memory starting from the address set in registers 0x62h and 63h.

SPACE

0x60h setup to run from SRAM Program Memory: Upon completion of programming, the following bits sequence needs to be completed in register 0x60h in order to enable the device to run properly out of SRAM:

7 6 5 4 3 2 1 0
PROG_SEL CPU_RST - PAR_EN RAM_EN PAR_SEL R/WZ CLR_PTR
1 → 0 1 → 0 0 0 → 1 0 → 1 1 → 0 0 0

Within 1ms of the completion of the above sequence, the device will complete a compatibility check on the SRAM

If the SRAM load is determined to be “Valid”: Register 0x41h will have a value between 0x01h and 0xFEh, and the device will return to normal operation.

If the SRAM load is determined to be “Invalid”:

• 0x41h will be set to 0xFFh

• The RAM_EN bit will be internally cleared

• The device will operating in “safe mode” until another programming attempt is completed