SLVSF02D March 2019 – May 2020 TPS23881
COMMAND = 08h with 1 Data Byte, Read only
COMMAND = 09h with 1 Data Byte, Clear on Read
Active high, each bit corresponds to a particular event that occurred.
Each bit xxx1-4 represents an individual channel.
A read at each location (08h or 09h) returns the same register data with the exception that the Clear on Read command clears all bits of the register. These bits are cleared when channel-n is turned off.
If this register is causing the INT pin to be activated, this Clear on Read will release the INT pin.
Any active bit will have an impact on the Interrupt register as indicated in the Interrupt register description.
|LEGEND: R/W = Read/Write; R = Read only; ; CR = Clear on Read, -n = value after reset|
|7–4||ILIM4–ILIM1||R or CR||0||Indicates that a tLIM fault occurred, which means the channel has limited its output current to ILIM or the folded back ILIM for more than tLIM.
1 = tLIM fault occurred
0 = No tLIM fault occurred
|3–0||STRT4–STRT1||R or CR||0||Indicates that a tSTART fault occurred during turn on.
1 = tSTART fault or class/detect error occurred
0 = No tSTART fault or class/detect error occurred
For 4-pair wired Ports:
The ILIMn bits will be updated individually as the status changes for each channel.
The STRTn bits will be updated individually as the status changes for each channel
When a Start Fault is reported and the PECn bit in Power Event register is set, then there is an Inrush fault.
When a Start Fault is reported and the PECn bit is not set, then the Power-On Fault register (0x24h) will indicate the cause of the fault.
In AUTO mode, STRTn faults will not be reported and register 0x24h will not be updated due to invalid discovery results.
In the event a singular channel of a 4-pair dual signature PD is turned off due to a ILIM fault or STRT fault, power may be reapplied to that channel by setting the PWON bit in 0x19h provided the detection and classification are still valid and the Power Allocation settings in 0x29 are sufficient based on the assigned classification of the powered channel.
Inrush Fault (STRTn) Handling on 4-Pair wired ports:
For 4-pair wired ports with single signature PDs connected, the inrush behavior will vary based on assigned classification given during turn on:
For 4P SS PD with an assigned classification of Class 6 or lower:
One channel will go through inrush while the second channel remains idle
If no STRT fault is detected at the end of inrush, the second channel will immediately turn on, and the PGn bits will be set
If a STRT fault is detected at the end of inrush, the secondary channel will remain off and the primary will be disabled, and a 1 sec cool-down period will be initiated on both channels. Both STRTn bits will be set.
For 4P SS PD with an assigned classification of Class 7 or 8:
Both channels will go through inrush in parallel
If no STRT fault is detected at the end of inrush on either channel, the PGn bits will be set and the port will remain powered.
If a STRT fault is detected at the end of inrush on either channel, both channels will be disabled, and a 1 sec cool-down period will be initiated on both channels. Both STRTn bits will be set.
For 4-pair wired ports with dual signature PDs connected, both channel will operate independent of the other. Each will do perform inrush control during startup and if either channel faults, the remaining channel will be unaffected.