SLVSF02D March 2019 – May 2020 TPS23881
COMMAND = 0Ah with 1 Data Byte, Read only
COMMAND = 0Bh with 1 Data Byte, Clear on Read
Active high, each bit corresponds to a particular event that occurred.
A read at each location (0Ah or 0Bh) returns the same register data with the exception that the Clear on Read command clears all bits of the register.
If this register is causing the INT pin to be activated, this Clear on Read will release the INT pin.
Any active bit will have an impact on the Interrupt register as indicated in the Interrupt register description.
|LEGEND: R/W = Read/Write; R = Read only; ; CR = Clear on Read, -n = value after reset|
|7||TSD||R or CR||0 / P||Indicates that a thermal shutdown occurred. When there is thermal shutdown, all channels are turned off and are put in OFF mode. The TPS23881 internal circuitry continues to operate however, including the ADCs. Note that at as soon as the internal temperature has decreased below the low threshold, the channels can be turned back ON regardless of the status of the TSD bit.
1 = Thermal shutdown occurred
0 = No thermal shutdown occurred
|6||VDUV||R or CR||1 / P||Indicates that a VDD UVLO occurred.
1 = VDD UVLO occurred
0 = No VDD UVLO occurred
|5||VDWRN||R or CR||1 / P||Indicates that the VDD has fallen under the UVLO warning threshold.
1 = VDD UV Warning occurred
0 = No VDD UV warning occurred
|4||VPUV||R or CR||1 / P||Indicates that a VPWR undervoltage occurred.
1 = VPWR undervoltage occurred
0 = No VPWR undervoltage occurred
|3||PCUT34||R or CR||0 / 0||Indicates that a 4-Pair Summed PCUT fault occurred on channels 3 and 4.
1 = 4-Pair Summed PCUT fault occurred on channels 3 and 4
0 = No Summed PCUT fault occurred
|2||PCUT12||R or CR||0 / 0||Indicates that a 4-Pair Summed PCUT fault occurred on channels 1 and 2.
1 = 4-Pair Summed PCUT fault occurred on channels 1 and 2
0 = No Summed PCUT fault occurred
|1||OSSE||R or CR||0 / 0||Indicates that an OSS Event occurred
1 = one or more channels with a group of 4 were disabled due to the assertion of the OSS pin or provided 3-bit OSS code
0 = No OSS events occurred
|0||RAMFLT||R or CR||0 / 0||Indicates that a SRAM fault has occurred
1 = SRAM fault occurred
0 = No SRAM fault occurred
The RST condition of "P" indicates that the previous state of these bits will be preserved following a device reset using the RESET pin. Thus, pulling the RESET input low will not clear the TSD, VDUV, VDWRN, or VPUV bits.
While the VPUV bit is set, any PWONn commands will be ignored until VVPWR > 30 V.
During VPUV undervoltage condition, the Detection Event register (CLSCn, DETCn) is not cleared, unless VPWR also falls below the VPWR UVLO falling threshold (approximately18 V).
A clear on Read will not effectively clear VDUV bit as long as the VPWR undervoltage condition is maintained.
In 1-bit mode (MbitPrty = 0 in reg 0x17), the OSSE bit will be set anytime a channel within a group of 4 has OSS enabled and the OSS pin is asserted.
In 3-bit mode (MbitPrty = 1 in reg 0x17), the OSSE bit will be set anytime a 3-bit priority code is sent that is equal to or greater than the MBPn settings in registers 0x27 and 0x28 channel for a group of 4 channels.
For a 4-pair wired port, if 4P PCUT is disabled (4PPCTxx = 0 in 0x2D), the port will not be automatically turned off during a 4P-PCUT fault condition. However, the PCUTnn fault bits will still be operational, with a fault timeout equal to tOVLD. Also, if a Clear on Read is done at the Fault Event register, the PCUTnn bit is reset, and the associated summed PCUT counter is reset. Only the Channels reporting such interrupt have their counter cleared by the CoR operation. Also, clearing a PCUT fault has no impact on TLIM counter.