SLVSG51A April 2021 – February 2022 TPS23882B
PRODUCTION DATA
COMMAND = 29h with 1 Data Byte, Read/Write
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Rsvrd | MC34_2 | MC34_1 | MC34_0 | Rsvrd | MC12_2 | MC12_1 | MC12_0 |
R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W–0 |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description | ||||||
---|---|---|---|---|---|---|---|---|---|---|
7 , 3 | Rsvrd | R/W | 0 | Reserved | ||||||
6 - 4 , 2 - 0 | MCnn_2-0 | R/W | 0 | MCnn_2-0: Port Power Allocation bits. These bits set the maximum power classification level that a given channel is allowed to power on In semiauto mode these bits need to be set prior to issuing a PWONn command, while in auto mode these bits need to be set prior to setting the DETE and CLE bits in 0x14. |
MCnn_2 | MCnn_1 | MCnn_0 | Power Allocation |
---|---|---|---|
0 | 0 | 0 | 2-Pair 15.4W |
0 | 0 | 1 | 2-Pair 4 W |
0 | 1 | 0 | 2-Pair 7 W |
0 | 1 | 1 | 2-Pair 30W |
1 | x | x | Reserved |
The Power Allocation (0x29h) value needs to be set prior to issuing a PWON command in semiauto or auto modes, and prior to setting the DETE and CLE bits in auto mode. Any changes to the Power Allocation value after a PWON command is given may be ignored.
For 2-Pair wired ports, the MCnn_2-0 bits set the power allocation settings for both channels 1 and 2 and 3 and 4 concurrently.
It is possible to have channels 3 and 4 set to 15.4W while channels 1 and 2 are set to 30W, but it is not possible to have different power allocation settings between channels 1 and 2 or 3 and 4
Setting register 0x29 to the 4 W Power Allocation configuration will only allow Class 1 PDs to be powered. Attempts to power any other class PDs will result in an insufficient power fault
Setting register 0x29 to the 7 W Power Allocation configuration will only allow Class 1 & 2 PDs to be powered. Attempts to power a class 3 or 4+ PDs will result in an insufficient power fault