SLVSG51A April   2021  – February 2022 TPS23882B

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1. 6.1 Detailed Pin Description
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Timing Diagrams
  9. 9 Detailed Description
    1. 9.1 Overview
      1. 9.1.1 Operating Modes
        1. 9.1.1.1 Auto
        2. 9.1.1.2 Autonomous
        3. 9.1.1.3 Semiauto
        4. 9.1.1.4 Manual and Diagnostic
        5. 9.1.1.5 Power Off
      2. 9.1.2 PoE Compliance Terminology
      3. 9.1.3 PoE 2 Type-3 2-Pair PoE
      4. 9.1.4 Requested Class Versus Assigned Class
      5. 9.1.5 Power Allocation and Power Demotion
      6. 9.1.6 Programmable SRAM
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Port Remapping
      2. 9.3.2 Port Power Priority
      3. 9.3.3 Analog-to-Digital Converters (ADC)
      4. 9.3.4 I2C Watchdog
      5. 9.3.5 Current Foldback Protection
    4. 9.4 Device Functional Modes
      1. 9.4.1 Detection
      2. 9.4.2 Classification
      3. 9.4.3 DC Disconnect
    5. 9.5 I2C Programming
      1. 9.5.1 I2C Serial Interface
    6. 9.6 Register Maps
      1. 9.6.1 Complete Register Set
      2. 9.6.2 Detailed Register Descriptions
        1. 9.6.2.1  INTERRUPT Register
        2. 9.6.2.2  INTERRUPT MASK Register
        3. 9.6.2.3  POWER EVENT Register
        4. 9.6.2.4  DETECTION EVENT Register
        5. 9.6.2.5  FAULT EVENT Register
        6. 9.6.2.6  START/ILIM EVENT Register
        7. 9.6.2.7  SUPPLY and FAULT EVENT Register
          1. 9.6.2.7.1 Detected SRAM Faults and "Safe Mode"
        8. 9.6.2.8  CHANNEL 1 DISCOVERY Register
        9. 9.6.2.9  CHANNEL 2 DISCOVERY Register
        10. 9.6.2.10 CHANNEL 3 DISCOVERY Register
        11. 9.6.2.11 CHANNEL 4 DISCOVERY Register
        12. 9.6.2.12 POWER STATUS Register
        13. 9.6.2.13 PIN STATUS Register
          1. 9.6.2.13.1 AUTONOMOUS MODE
        14. 9.6.2.14 OPERATING MODE Register
        15. 9.6.2.15 DISCONNECT ENABLE Register
        16. 9.6.2.16 DETECT/CLASS ENABLE Register
        17. 9.6.2.17 Power Priority / 2Pair PCUT Disable Register Name
        18. 9.6.2.18 TIMING CONFIGURATION Register
        19. 9.6.2.19 GENERAL MASK Register
        20. 9.6.2.20 DETECT/CLASS RESTART Register
        21. 9.6.2.21 POWER ENABLE Register
        22. 9.6.2.22 RESET Register
        23. 9.6.2.23 ID Register
        24. 9.6.2.24 Connection Check and Auto Class Status Register
        25. 9.6.2.25 2-Pair Police Ch-1 Configuration Register
        26. 9.6.2.26 2-Pair Police Ch-2 Configuration Register
        27. 9.6.2.27 2-Pair Police Ch-3 Configuration Register
        28. 9.6.2.28 2-Pair Police Ch-4 Configuration Register
        29. 9.6.2.29 Capacitance (Legacy PD) Detection
        30. 9.6.2.30 Power-on Fault Register
        31. 9.6.2.31 PORT RE-MAPPING Register
        32. 9.6.2.32 Channels 1 and 2 Multi Bit Priority Register
        33. 9.6.2.33 Channels 3 and 4 Multi Bit Priority Register
        34. 9.6.2.34 Port Power Allocation Register
        35. 9.6.2.35 TEMPERATURE Register
        36. 9.6.2.36 INPUT VOLTAGE Register
        37. 9.6.2.37 CHANNEL 1 CURRENT Register
        38. 9.6.2.38 CHANNEL 2 CURRENT Register
        39. 9.6.2.39 CHANNEL 3 CURRENT Register
        40. 9.6.2.40 CHANNEL 4 CURRENT Register
        41. 9.6.2.41 CHANNEL 1 VOLTAGE Register
        42. 9.6.2.42 CHANNEL 2 VOLTAGE Register
        43. 9.6.2.43 CHANNEL 3 VOLTAGE Register
        44. 9.6.2.44 CHANNEL 4 VOLTAGE Register
        45. 9.6.2.45 2x FOLDBACK SELECTION Register
        46.       93
        47. 9.6.2.46 FIRMWARE REVISION Register
        48. 9.6.2.47 I2C WATCHDOG Register
        49. 9.6.2.48 DEVICE ID Register
        50. 9.6.2.49 CHANNEL 1 DETECT RESISTANCE Register
        51. 9.6.2.50 CHANNEL 2 DETECT RESISTANCE Register
        52. 9.6.2.51 CHANNEL 3 DETECT RESISTANCE Register
        53. 9.6.2.52 CHANNEL 4 DETECT RESISTANCE Register
        54. 9.6.2.53 CHANNEL 1 DETECT CAPACITANCE Register
        55. 9.6.2.54 CHANNEL 2 DETECT CAPACITANCE Register
        56. 9.6.2.55 CHANNEL 3 DETECT CAPACITANCE Register
        57. 9.6.2.56 CHANNEL 4 DETECT CAPACITANCE Register
        58. 9.6.2.57 CHANNEL 1 ASSIGNED CLASS Register
        59. 9.6.2.58 CHANNEL 2 ASSIGNED CLASS Register
        60. 9.6.2.59 CHANNEL 3 ASSIGNED CLASS Register
        61. 9.6.2.60 CHANNEL 4 ASSIGNED CLASS Register
        62. 9.6.2.61 AUTO CLASS CONTROL Register
        63. 9.6.2.62 CHANNEL 1 AUTO CLASS POWER Register
        64. 9.6.2.63 CHANNEL 2 AUTO CLASS POWER Register
        65. 9.6.2.64 CHANNEL 3 AUTO CLASS POWER Register
        66. 9.6.2.65 CHANNEL 4 AUTO CLASS POWER Register
        67. 9.6.2.66 ALTERNATIVE FOLDBACK Register
        68. 9.6.2.67 SRAM CONTROL Register
          1. 9.6.2.67.1 SRAM START ADDRESS (LSB) Register
          2. 9.6.2.67.2 SRAM START ADDRESS (MSB) Register
          3. 9.6.2.67.3 118
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Autonomous Operation
      2. 10.1.2 Introduction to PoE
        1. 10.1.2.1 2-Pair Versus 4-Pair Power and the New IEEE802.3bt Standard
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Connections on Unused Channels
        2. 10.2.2.2 Power Pin Bypass Capacitors
        3. 10.2.2.3 Per Port Components
        4. 10.2.2.4 System Level Components (not Shown in the Schematic Diagrams)
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
    1. 11.1 VDD
    2. 11.2 VPWR
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Kelvin Current Sensing Resistors
      2.      138
    2. 12.2 Layout Example
      1. 12.2.1 Component Placement and Routing Guidelines
        1. 12.2.1.1 Power Pin Bypass Capacitors
        2. 12.2.1.2 Per-Port Components
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Support Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.6.2.18 TIMING CONFIGURATION Register

COMMAND = 16h with 1 Data Byte, Read/Write

Bit Descriptions: These bits define the timing configuration for all four channels.

Figure 9-23 TIMING CONFIGURATION Register Format
76543210
TLIMTSTARTTOVLDTMPDO
R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9-23 TIMING CONFIGURATION Register Field Descriptions
BitFieldTypeResetDescription
7 –6TLIMR/W0ILIM fault timing, which is the output current limit time duration before channel turn off.

When a 2xFBn bit in register 0x40 = 0, the tLIM used for the associated channel is always the nominal value (about 60 ms).

This timer is active and increments to the settings defined below after expiration of the TSTART time window and when the channel is limiting its output current to ILIM. If the ILIM counter is allowed to reach the programmed time-out duration specified below, the channel will be powered off. The 1-second cool down timer is then started, and the channel can not be turned-on until the counter has reached completion.

In other circumstances (ILIM time-out has not been reached), while the channel current is below ILIM, the same counter decrements at a rate 1/16th of the increment rate. The counter does not decrement below zero. The ILIM counter is also cleared in the event of a turn off due to a Power Enable or Reset command, a DC disconnect event or the OSS input.

Note that in the event the TLIM setting is changed while this timer is already active for a channel, this timer is automatically reset then restarted with the new programmed time-out duration.

Note that at the end of cool down cycle, when in semiauto mode, a detection cycle is automatically restarted if the detect enable bit is set. Also note that the cool down time count is immediately canceled with a reset command, or if the OFF or Manual mode is selected.

If 2xFBn bit is asserted in register 0x40, then tLIM for associated channel is programmable with the following selection:

TLIMMinimum tLIM (ms)
0058
0115
1010
116
5-4TSTART

(or TINRUSH)

R/W0START fault timing, which is the maximum allowed overcurrent time during inrush. If at the end of TSTART period the current is still limited to IInrush, the channel is powered off.

This is followed by a 1-second cool down period, during which the channel can not be turned-on

Note that at the end of cool down cycle, when in semiauto mode, a detection cycle is automatically restarted if the class and detect enable bits are set.

Note that in the event the TSTART setting is changed while this timer is already active for a channel, this new setting is ignored and will be applied only next time the channel is turned ON.

The selection is as following:

TSTARTNominal tSTART (ms)
0060
0130
10120
11Reserved
3–2TOVLDR/W0PCUT fault timing, which is the overcurrent time duration before turn off. This timer is active and increments to the settings defined below after expiration of the TSTART time window and when the current meets or exceeds PCUT, or when it is limited by the current foldback. If the PCUT counter is allowed to reach the programmed time-out duration specified below, the channel will be powered off. The 1-second cool down timer is then started, and the channel can not be turned-on until the counter has reached completion.

In other circumstances (PCUT time-out has not been reached), while the current is below PCUT, the same counter decrements at a rate 1/16th of the increment rate. The counter does not decrement below zero. The PCUT counter is also cleared in the event of a turn off due to a Power Enable or Reset command, a DC disconnect event or the OSS input

Note that in the event the TOVLD setting is changed while this timer is already active for a channel, this timer is automatically reset then restarted with the new programmed time-out duration.

Note that at the end of cool down cycle, when in semiauto mode, a detection cycle is automatically restarted if the detect enable bit is set. Also note that the cool down time count is immediately canceled with a reset command, or if the OFF or Manual mode is selected.

Note that if a DCUTn bit is high in the Power Priority/PCUT Disable register, the PCUT fault timing for the associated channel is still active. However, even though the channel will not be turned off when the tOVLD time expires, the PCUT fault bits will still be set.

The selection is as following:

TOVLD Nominal tOVLD (ms)
0060
0130
10120
11240
1–0TMPDOR/W0Disconnect delay, which is the time to turn off a channel once there is a disconnect condition, and if the dc disconnect detect method has been enabled.

The TDIS counter is reset each time the current goes continuously higher than the disconnect threshold for nominally 15 ms.

The counter does not decrement below zero.

The selection is as following:

TMPDONominal tMPDO (ms)
00360
0190
10180
11180

Note:

The PGn and PEn bits (Power Status register) are cleared when there is a TLIM, TOVLD, TMPDO, or TSTART fault condition.

Note:

The settings for tLIM set the minimum timeout based on the IEEE compliance requirements.