SLVSG51A April   2021  – February 2022 TPS23882B

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1. 6.1 Detailed Pin Description
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Timing Diagrams
  9. 9 Detailed Description
    1. 9.1 Overview
      1. 9.1.1 Operating Modes
        1. 9.1.1.1 Auto
        2. 9.1.1.2 Autonomous
        3. 9.1.1.3 Semiauto
        4. 9.1.1.4 Manual and Diagnostic
        5. 9.1.1.5 Power Off
      2. 9.1.2 PoE Compliance Terminology
      3. 9.1.3 PoE 2 Type-3 2-Pair PoE
      4. 9.1.4 Requested Class Versus Assigned Class
      5. 9.1.5 Power Allocation and Power Demotion
      6. 9.1.6 Programmable SRAM
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Port Remapping
      2. 9.3.2 Port Power Priority
      3. 9.3.3 Analog-to-Digital Converters (ADC)
      4. 9.3.4 I2C Watchdog
      5. 9.3.5 Current Foldback Protection
    4. 9.4 Device Functional Modes
      1. 9.4.1 Detection
      2. 9.4.2 Classification
      3. 9.4.3 DC Disconnect
    5. 9.5 I2C Programming
      1. 9.5.1 I2C Serial Interface
    6. 9.6 Register Maps
      1. 9.6.1 Complete Register Set
      2. 9.6.2 Detailed Register Descriptions
        1. 9.6.2.1  INTERRUPT Register
        2. 9.6.2.2  INTERRUPT MASK Register
        3. 9.6.2.3  POWER EVENT Register
        4. 9.6.2.4  DETECTION EVENT Register
        5. 9.6.2.5  FAULT EVENT Register
        6. 9.6.2.6  START/ILIM EVENT Register
        7. 9.6.2.7  SUPPLY and FAULT EVENT Register
          1. 9.6.2.7.1 Detected SRAM Faults and "Safe Mode"
        8. 9.6.2.8  CHANNEL 1 DISCOVERY Register
        9. 9.6.2.9  CHANNEL 2 DISCOVERY Register
        10. 9.6.2.10 CHANNEL 3 DISCOVERY Register
        11. 9.6.2.11 CHANNEL 4 DISCOVERY Register
        12. 9.6.2.12 POWER STATUS Register
        13. 9.6.2.13 PIN STATUS Register
          1. 9.6.2.13.1 AUTONOMOUS MODE
        14. 9.6.2.14 OPERATING MODE Register
        15. 9.6.2.15 DISCONNECT ENABLE Register
        16. 9.6.2.16 DETECT/CLASS ENABLE Register
        17. 9.6.2.17 Power Priority / 2Pair PCUT Disable Register Name
        18. 9.6.2.18 TIMING CONFIGURATION Register
        19. 9.6.2.19 GENERAL MASK Register
        20. 9.6.2.20 DETECT/CLASS RESTART Register
        21. 9.6.2.21 POWER ENABLE Register
        22. 9.6.2.22 RESET Register
        23. 9.6.2.23 ID Register
        24. 9.6.2.24 Connection Check and Auto Class Status Register
        25. 9.6.2.25 2-Pair Police Ch-1 Configuration Register
        26. 9.6.2.26 2-Pair Police Ch-2 Configuration Register
        27. 9.6.2.27 2-Pair Police Ch-3 Configuration Register
        28. 9.6.2.28 2-Pair Police Ch-4 Configuration Register
        29. 9.6.2.29 Capacitance (Legacy PD) Detection
        30. 9.6.2.30 Power-on Fault Register
        31. 9.6.2.31 PORT RE-MAPPING Register
        32. 9.6.2.32 Channels 1 and 2 Multi Bit Priority Register
        33. 9.6.2.33 Channels 3 and 4 Multi Bit Priority Register
        34. 9.6.2.34 Port Power Allocation Register
        35. 9.6.2.35 TEMPERATURE Register
        36. 9.6.2.36 INPUT VOLTAGE Register
        37. 9.6.2.37 CHANNEL 1 CURRENT Register
        38. 9.6.2.38 CHANNEL 2 CURRENT Register
        39. 9.6.2.39 CHANNEL 3 CURRENT Register
        40. 9.6.2.40 CHANNEL 4 CURRENT Register
        41. 9.6.2.41 CHANNEL 1 VOLTAGE Register
        42. 9.6.2.42 CHANNEL 2 VOLTAGE Register
        43. 9.6.2.43 CHANNEL 3 VOLTAGE Register
        44. 9.6.2.44 CHANNEL 4 VOLTAGE Register
        45. 9.6.2.45 2x FOLDBACK SELECTION Register
        46.       93
        47. 9.6.2.46 FIRMWARE REVISION Register
        48. 9.6.2.47 I2C WATCHDOG Register
        49. 9.6.2.48 DEVICE ID Register
        50. 9.6.2.49 CHANNEL 1 DETECT RESISTANCE Register
        51. 9.6.2.50 CHANNEL 2 DETECT RESISTANCE Register
        52. 9.6.2.51 CHANNEL 3 DETECT RESISTANCE Register
        53. 9.6.2.52 CHANNEL 4 DETECT RESISTANCE Register
        54. 9.6.2.53 CHANNEL 1 DETECT CAPACITANCE Register
        55. 9.6.2.54 CHANNEL 2 DETECT CAPACITANCE Register
        56. 9.6.2.55 CHANNEL 3 DETECT CAPACITANCE Register
        57. 9.6.2.56 CHANNEL 4 DETECT CAPACITANCE Register
        58. 9.6.2.57 CHANNEL 1 ASSIGNED CLASS Register
        59. 9.6.2.58 CHANNEL 2 ASSIGNED CLASS Register
        60. 9.6.2.59 CHANNEL 3 ASSIGNED CLASS Register
        61. 9.6.2.60 CHANNEL 4 ASSIGNED CLASS Register
        62. 9.6.2.61 AUTO CLASS CONTROL Register
        63. 9.6.2.62 CHANNEL 1 AUTO CLASS POWER Register
        64. 9.6.2.63 CHANNEL 2 AUTO CLASS POWER Register
        65. 9.6.2.64 CHANNEL 3 AUTO CLASS POWER Register
        66. 9.6.2.65 CHANNEL 4 AUTO CLASS POWER Register
        67. 9.6.2.66 ALTERNATIVE FOLDBACK Register
        68. 9.6.2.67 SRAM CONTROL Register
          1. 9.6.2.67.1 SRAM START ADDRESS (LSB) Register
          2. 9.6.2.67.2 SRAM START ADDRESS (MSB) Register
          3. 9.6.2.67.3 118
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Autonomous Operation
      2. 10.1.2 Introduction to PoE
        1. 10.1.2.1 2-Pair Versus 4-Pair Power and the New IEEE802.3bt Standard
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Connections on Unused Channels
        2. 10.2.2.2 Power Pin Bypass Capacitors
        3. 10.2.2.3 Per Port Components
        4. 10.2.2.4 System Level Components (not Shown in the Schematic Diagrams)
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
    1. 11.1 VDD
    2. 11.2 VPWR
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Kelvin Current Sensing Resistors
      2.      138
    2. 12.2 Layout Example
      1. 12.2.1 Component Placement and Routing Guidelines
        1. 12.2.1.1 Power Pin Bypass Capacitors
        2. 12.2.1.2 Per-Port Components
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Support Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.6.1 Complete Register Set

Table 9-3 Main Registers
Cmd CodeRegister or
Command Name		I2C
R/W		Data
Byte		RST StateBits Description
INTERRUPTS
00hINTERRUPTRO11000,0000b(1)SUPFSTRTFIFAULTCLASCDETCDISFPGCPEC
01hINTERRUPT MASKR/W11000,0000b
SUMSKSTMSKIFMSKCLMSKDEMSKDIMSKPGMSKPEMSK
EVENT
02hPOWER EVENTRO10000,0000bPower Good status changePower Enable status change
03hCoR1PGC4PGC3PGC2PGC1PEC4PEC3PEC2PEC1
04hDETECTION EVENTRO10000,0000bClassificationDetection
05hCoR1CLSC4CLSC3CLSC2CLSC1DETC4DETC3DETC2DETC1
06hFAULT EVENTRO10000,0000bDisconnect occurredPCUT fault occurred
07hCoR1DISF4DISF3DISF2DISF1PCUT4PCUT3PCUT2PCUT1
08hSTART/ILIM EVENTRO10000,0000bILIM fault occurredSTART fault occurred
09hCoR1ILIM4ILIM3ILIM2ILIM1STRT4STRT3STRT2STRT1
0AhSUPPLY/FAULT EVENTRO10111,0000b(2)TSDVDUVVDWRNVPUVRsvrdRsvrdOSSERAMFLT
0BhCoR1
STATUS
0ChCHANNEL 1 DISCOVERYRO10000,0000bRequested CLASS Channel 1DETECT Channel 1
0DhCHANNEL 2 DISCOVERYRO10000,0000bRequested CLASS Channel 2DETECT Channel 2
0EhCHANNEL 3 DISCOVERYRO10000,0000bRequested CLASS Channel 3DETECT Channel 3
0FhCHANNEL 4 DISCOVERYRO10000,0000bRequested CLASS Channel 4DETECT Channel 4
10hPOWER STATUSRO10000,0000bPG4PG3PG2PG1PE4PE3PE2PE1
11hPIN STATUSRO10,A[4:0],0,0RsvdSLA4SLA3SLA2SLA1SLA0RsvdRsvd
CONFIGURATION
12hOPERATING MODER/W10000,0000bChannel 4 ModeChannel 3 ModeChannel 2 ModeChannel 1 Mode
13hDISCONNECT ENABLER/W10000 ,1111bRsvdRsvdRsvdRsvdDCDE4DCDE3DCDE2DCDE1
14hDETECT/CLASS ENABLER/W10000,0000bCLE4CLE3CLE2CLE1DETE4DETE3DETE2DETE1
15hPWRPR/PCUT DISABLER/W10000,0000bOSS4OSS3OSS2OSS1DCUT4DCUT3DCUT2DCUT1
16hTIMING CONFIGR/W10000,0000bTLIMTSTARTTOVLDTMPDO
17hGENERAL MASKR/W11000,0000bINTENRsvdnbitACCMbitPrtyCLCHEDECHERsvd
PUSH BUTTONS
18hDETECT/CLASS RestartWO10000,0000bRCL4RCL3RCL2RCL1RDET4RDET3RDET2RDET1
19hPOWER ENABLEWO10000,0000bPOFF4POFF3POFF2POFF1PWON4PWON3PWON2PWON1
1AhRESETWO10000,0000bCLRAINCLINPRsvdRESALRESP4RESP3RESP2RESP1
GENERAL/SPECIALIZED
1BhIDRO10101,0101bMFR IDIC Version
1ChAUTOCLASSR/O10000,0000bAC4AC3AC2AC1RsvrdRsvrdRsvrdRsvrd
1DhRESERVEDR/W10000,0000bRsrvd
1Eh2P POLICE 1 CONFIGR/W11111,1111b2-Pair POLICE Channel 1
1Fh2P POLICE 2 CONFIGR/W11111,1111b2-Pair POLICE Channel 2
20h2P POLICE 3 CONFIGR/W11111,1111b2-Pair POLICE Channel 3
21h2P POLICE 4CONFIGR/W11111,1111b2-Pair POLICE Channel 4
22hCAP MEASUREMENT(3)R/W10000,0000bRsvdCDET4RsvdCDET3RsvdCDET2RsvdCDET1
23hReservedR/W10000,0000bRsvdRsvdRsvdRsvdRsvdRsvdRsvdRsvd
24hPower-on FAULTRO10000,0000bPF Channel 4PF Channel 3PF Channel 2PF Channel 1
25hCoR1
26hRE-MAPPINGR/W11110,0100bPhysical re-map Logical Port 4Physical re-map Logical Port 3Physical re-map Logical Port 2Physical re-map Logical Port 1
27hMulti-Bit Priority 21R/W10000,0000bRsvdChannel 2RsvdChannel 1
28hMulti-Bit Priority 43R/W10000,0000bRsvdChannel 4RsvdChannel 3
29hPort Power AllocationR/W10000,0000bRsvdMC34RsvdMC12
2A - 2BhReservedR/W11111,1111bRsrvd
2ChTEMPERATURERO10000,0000bTemperature (bits 7 to 0)
2DhReservedR/W10000,0000bRsvdRsvdRsvdRsvdRsvdRsvdRsvdRsvd
2EhINPUT VOLTAGERO20000,0000bInput Voltage: LSByte
2FhRO0000,0000bRsvdRsvdInput Voltage: MSByte (bits 13 to 8)
EXTENDED REGISTER SET – PARAMETRIC MEASUREMENT
30hChannel 1 CURRENTRO20000,0000bChannel 1 Current: LSByte
31hRO0000,0000bRsvdRsvdChannel 1 Current: MSByte (bits 13 to 8)
32hChannel 1 VOLTAGERO20000,0000bChannel 1 Voltage: LSByte
33hRO0000,0000bRsvdRsvdChannel 1 Voltage: MSByte (bits 13 to 8)
(1) SUPF bit reset state shown is at Power up only
(2) VDUV, VPUV and VDWRN bits reset state shown is at Power up only
(3) Capacitance Measurement is only supported if SRAM code is programmed
Table 9-4 Main Registers
Cmd CodeRegister or
Command Name		I2C R/WData ByteRST StateBits Description
34hChannel 2 CURRENTRO20000,0000bChannel 2 Current: LSByte
35hRO0000,0000bRsvdRsvdChannel 2 Current: MSByte (bits 13 to 8)
36hChannel 2 VOLTAGERO20000,0000bChannel 2 Voltage: LSByte
37hRO0000,0000bRsvdRsvdChannel 2 Voltage: MSByte (bits 13 to 8)
38hChannel 3 CURRENTRO20000,0000bChannel 3 current: LSByte
39hRO0000,0000bRsvdRsvdChannel 3 Current: MSByte (bits 13 to 8)
3AhChannel 3 VOLTAGERO20000,0000bChannel 3 Voltage: LSByte
3BhRO0000,0000bRsvdRsvdChannel 3 Voltage: MSByte (bits 13 to 8)
3ChChannel 4 CURRENTRO20000,0000bChannel 4 current: LSByte
3DhRO0000,0000bRsvdRsvdChannel 4 Current: MSByte (bits 13 to 8)
3EhChannel 4 VOLTAGERO20000,0000bChannel 4 Voltage: LSByte
3FhRO0000,0000bRsvdRsvdChannel 4 Voltage: MSByte (bits 13 to 8)
CONFIGURATION/OTHERS
40hCHANNEL FOLDBACKR/W10000,0000b2xFB42xFB32xFB22xFB1

MPOL4

MPOL3

MPOL2

MPOL1

41hFIRMWARE REVISIONRO1RRRR,RRRRbFirmware Revision
42hI2C WATCHDOGR/W10001,0110bRsvdRsvdRsvdWatchdog DisableWDS
43hDEVICE IDRO10011,0100bDevice ID numberSilicon Revision number
SIGNATURE MEASUREMENTS
44hCh1 DETECT RESISTANCERO10000,0000bChannel 1 Resistance
45hCh2 DETECT RESISTANCERO10000,0000bChannel 2 Resistance
46hCh3 DETECT RESISTANCERO10000,0000bChannel 3 Resistance
47hCh4 DETECT RESISTANCERO10000,0000bChannel 4 Resistance
48hCh1 CAP MEASUREMENT(3)RO10000,0000bChannel 1 Capacitance
49hCh2 CAP MEASUREMENT(3)RO10000,0000bChannel 2 Capacitance
4AhCh3 CAP MEASUREMENT(3)RO10000,0000bChannel 3 Capacitance
4BhCh4 CAP MEASUREMENT(3)RO10000,0000bChannel 4 Capacitance
ASSIGNED CHANNEL STATUS
4ChASSIGNED CLASS CHANNEL 1RO10000,0000bAssigned CLASS Channel 1Previous CLASS Channel 1
4DhASSIGNED CLASS CHANNEL 2RO10000,0000bAssigned CLASS Channel 2Previous CLASS Channel 2
4EhASSIGNED CLASS CHANNEL 3RO10000,0000bAssigned CLASS Channel 3Previous CLASS Channel 3
4FhASSIGNED CLASS CHANNEL 4RO10000,0000bAssigned CLASS Channel 4Previous CLASS Channel 4
AUTOCLASS CONFIGURATION/MEASUREMENTS
50hAUTOCLASS CONTROLR/W10000,0000bMAC4MAC3MAC2MAC1AAC4AAC3AAC2AAC1
51hCHANNEL 1 AUTOCLASS PWRRO10000,0000bRsrvdChannel 1 AutoClass Power
52hCHANNEL 2 AUTOCLASS PWRRO10000,0000bRsrvdChannel 2 AutoClass Power
53hCHANNEL 3 AUTOCLASS PWRRO10000,0000bRsrvdChannel 3 AutoClass Power
54hCHANNEL 4 AUTOCLASS PWRRO10000,0000bRsrvdChannel 4 AutoClass Power
MISCELLANEOUS
55hALTERNATIVE FOLDBACKR/W10000,0000bALTFB4ALTFB3ALTFB2ALTFB1ALTIR4ALTIR3ALTIR2ALTIR1
56h - 5FhRESERVEDR/W10000,0000bRsrvdRsrvdRsrvdRsrvdRsrvdRsrvdRsrvdRsrvd
SRAM
60hSRAM CONTROLR/W10000,0000bPROG_SELCPU_RSTRsrvdPAR_ENRAM_ENPAR_SELRZ/WCLR_PTR
61hSRAM DATAR/W--SRAM DATA - Read and Write (continuous)
62hSTART ADDRESSR/W10000,0000bProgramming Start Address (LSB)
63hR/W10000,0000bProgramming Start Address (MSB)
64h - 6FhRESERVEDR/W10000,0000bRsrvdRsrvdRsrvdRsrvdRsrvdRsrvdRsrvdRsrvd