SLVSCL5A June   2014  – November 2020 TPS2559

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Timing Diagrams
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Thermal Sense
      2. 8.3.2 Overcurrent Protection
      3. 8.3.3 FAULT Response
    4. 8.4 Device Functional Modes
      1. 8.4.1 Operation with VIN Undervoltage Lockout (UVLO) Control
      2. 8.4.2 Operation with EN Control
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Step-by-Step Design Procedure
        2. 9.2.2.2 Input and Output Capacitance
        3. 9.2.2.3 Programming the Current-Limit Threshold
        4. 9.2.2.4 Design Above a Minimum Current Limit
        5. 9.2.2.5 Design Below a Maximum Current Limit
        6. 9.2.2.6 Accounting for Resistor Tolerance
        7. 9.2.2.7 Power Dissipation and Junction Temperature
        8. 9.2.2.8 Auto-Retry
        9. 9.2.2.9 Two-Level Current-Limit
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.4.2 Operation with EN Control

The logic enable controls the power switch and device supply current. The supply current is reduced to less than 2-μA when a logic low is present on EN. A logic high input on EN enables the driver, control circuits, and power switch. The enable input is compatible with both TTL and CMOS logic levels.