SLVSFJ9 September   2021 TPS25854-Q1 , TPS25855-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (Continued)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Switching Characteristics
    8. 8.8 Typical Characteristics
  9. 9 Parameter Measurement Information
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1  Power Down or Undervoltage Lockout
      2. 10.3.2  Input Overvoltage Protection (OVP) - Continuously Monitored
      3. 10.3.3  Buck Converter
      4. 10.3.4  FREQ/SYNC
      5. 10.3.5  Bootstrap Voltage (BOOT)
      6. 10.3.6  Minimum ON-time, Minimum OFF-time
      7. 10.3.7  Internal Compensation
      8. 10.3.8  Current Limit and Short Circuit Protection
        1. 10.3.8.1 USB Switch Programmable Current Limit (ILIM)
        2. 10.3.8.2 Cycle-by-Cycle Buck Current Limit
        3. 10.3.8.3 OUT Current Limit
      9. 10.3.9  Cable Compensation
      10. 10.3.10 Thermal Management With Temperature Sensing (TS) and OTSD
      11. 10.3.11 Thermal Shutdown
      12. 10.3.12 FAULT Indication
      13. 10.3.13 USB Specification Overview
      14. 10.3.14 USB Type-C® Basics
        1. 10.3.14.1 Configuration Channel
        2. 10.3.14.2 Detecting a Connection
        3. 10.3.14.3 Plug Polarity Detection
      15. 10.3.15 USB Port Operating Modes
        1. 10.3.15.1 USB Type-C® Mode
        2. 10.3.15.2 Dedicated Charging Port (DCP) Mode
          1. 10.3.15.2.1 DCP BC1.2 and YD/T 1591-2009
          2. 10.3.15.2.2 DCP Divider-Charging Scheme
          3. 10.3.15.2.3 DCP 1.2-V Charging Scheme
        3. 10.3.15.3 DCP Auto Mode
    4. 10.4 Device Functional Modes
      1. 10.4.1 Shutdown Mode
      2. 10.4.2 Active Mode
  11. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Applications
      1. 11.2.1 Design Requirements
      2. 11.2.2 Detailed Design Procedure
        1. 11.2.2.1 Output Voltage Setting
        2. 11.2.2.2 Switching Frequency
        3. 11.2.2.3 Inductor Selection
        4. 11.2.2.4 Output Capacitor Selection
        5. 11.2.2.5 Input Capacitor Selection
        6. 11.2.2.6 Bootstrap Capacitor Selection
        7. 11.2.2.7 Undervoltage Lockout Set-Point
        8. 11.2.2.8 Cable Compensation Set-Point
        9. 11.2.2.9 FAULT, POL, and THERM_WARN Resistor Selection
      3. 11.2.3 Application Curves
  12. 12Power Supply Recommendations
  13. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Layout Example
    3. 13.3 Ground Plane and Thermal Considerations
  14. 14Device and Documentation Support
    1. 14.1 Receiving Notification of Documentation Updates
    2. 14.2 Support Resources
    3. 14.3 Trademarks
    4. 14.4 Electrostatic Discharge Caution
    5. 14.5 Glossary
  15. 15Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

13.3 Ground Plane and Thermal Considerations

TI recommends to use one of the middle layers as a solid ground plane. Ground plane provides shielding for sensitive circuits and traces. Ground plane also provides a quiet reference potential for the control circuitry. The AGND and PGND pins must be connected to the ground plane using vias right next to the bypass capacitors. The PGND pin is connected to the source of the internal low-side MOSFET switch, and also connected directly to the grounds of the input and output capacitors. The PGND net contains noise at the switching frequency and can bounce due to load variations. The PGND trace, as well as VIN and SW traces, must be constrained to one side of the ground plane. The other side of the ground plane contains much less noise and must be used for sensitive routes.

TI recommends to provide adequate device heat sinking by using the PAD of the IC as the primary thermal path. Use a minimum 4 × 2 array of 12-mil thermal vias to connect the PAD to the system ground plane heat sink. The vias must be evenly distributed under the PAD. Use as much copper as possible, for system ground plane, on the top and bottom layers for the best heat dissipation. Use a four-layer board with the copper thickness for the four layers, starting from the top of 2 oz / 1 oz / 1 oz / 2 oz. Four layer boards with enough copper thickness provide low current conduction impedance, proper shielding, and lower thermal resistance.

The thermal characteristics of the TPS2585x-Q1 are specified using the parameter θJA, which characterizes the junction temperature of silicon to the ambient temperature in a specific system. Although the value of θJA is dependent on many variables, it still can be used to approximate the operating junction temperature of the device. To obtain an estimate of the device junction temperature, one can use the following relationship:

Equation 16. TJ = PD × θJA + TA

where

  • TJ = Junction temperature in °C
  • PD = VIN × IIN × (1 – Efficiency) – 1.1 × IOUT2 × DCR in Watt
  • DCR = Inductor DC parasitic resistance in Ω
  • θJA = Junction-to-ambient thermal resistance of the device in °C/W
  • TA = Ambient temperature in °C

The maximum operating junction temperature of the TPS2585x-Q1 is 150°C. θJA is highly related to PCB size and layout, as well as environmental factors such as heat sinking and air flow.