SLVSF62B November   2020  – September 2021 TPS25858-Q1 , TPS25859-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Switching Characteristics
    8. 8.8 Typical Characteristics
  9. 9 Parameter Measurement Information
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1  Power-Down or Undervoltage Lockout
      2. 10.3.2  Input Overvoltage Protection (OVP) - Continuously Monitored
      3. 10.3.3  Buck Converter
      4. 10.3.4  FREQ/SYNC
      5. 10.3.5  Bootstrap Voltage (BOOT)
      6. 10.3.6  Minimum ON-Time, Minimum OFF-Time
      7. 10.3.7  Internal Compensation
      8. 10.3.8  Selectable Output Voltage (VSET)
      9. 10.3.9  Current Limit and Short Circuit Protection
        1. 10.3.9.1 USB Switch Programmable Current Limit (ILIM)
        2. 10.3.9.2 Interlocking for Two-Level USB Switch Current Limit
        3. 10.3.9.3 Cycle-by-Cycle Buck Current Limit
        4. 10.3.9.4 OUT Current Limit
      10. 10.3.10 Cable Compensation
      11. 10.3.11 Thermal Management With Temperature Sensing (TS) and OTSD
      12. 10.3.12 Thermal Shutdown
      13. 10.3.13 USB Enable On and Off Control (TPS25859-Q1)
      14. 10.3.14 FAULT Indication (TPS25859-Q1)
      15. 10.3.15 USB Specification Overview
      16. 10.3.16 USB Type-C® Basics
        1. 10.3.16.1 Configuration Channel
        2. 10.3.16.2 Detecting a Connection
      17. 10.3.17 USB Port Operating Modes
        1. 10.3.17.1 USB Type-C® Mode
        2. 10.3.17.2 Dedicated Charging Port (DCP) Mode (TPS25858-Q1 Only)
          1. 10.3.17.2.1 DCP BC1.2 and YD/T 1591-2009
          2. 10.3.17.2.2 DCP Divider-Charging Scheme
          3. 10.3.17.2.3 DCP 1.2-V Charging Scheme
        3. 10.3.17.3 DCP Auto Mode (TPS25858-Q1)
    4. 10.4 Device Functional Modes
      1. 10.4.1 Shutdown Mode
      2. 10.4.2 Active Mode
  11. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Applications
      1. 11.2.1 Design Requirements
      2. 11.2.2 Detailed Design Procedure
        1. 11.2.2.1 Output Voltage Setting
        2. 11.2.2.2 Switching Frequency
        3. 11.2.2.3 Inductor Selection
        4. 11.2.2.4 Output Capacitor Selection
        5. 11.2.2.5 Input Capacitor Selection
        6. 11.2.2.6 Bootstrap Capacitor Selection
        7. 11.2.2.7 Undervoltage Lockout Set-Point
        8. 11.2.2.8 Cable Compensation Set-Point
      3. 11.2.3 Application Curves
  12. 12Power Supply Recommendations
  13. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Layout Example
    3. 13.3 Ground Plane and Thermal Considerations
  14. 14Device and Documentation Support
    1. 14.1 Receiving Notification of Documentation Updates
    2. 14.2 Support Resources
    3. 14.3 Trademarks
    4. 14.4 Electrostatic Discharge Caution
    5. 14.5 Glossary
  15. 15Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.7 Switching Characteristics

Over the recommended operating junction temperature range of -40 °C to 150 °C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SW (SW PIN)
TON_MIN Minimum turnon-time 84 ns
TON_MAX Maximum turnon-time, HS timeout in dropout 6 µs
TOFF_MIN Minimum turnoff time 81 ns
Dmax Maximum switch duty cycle 98 %
TIMING RESISTOR AND INTERNAL CLOCK
fSW_RANGE Switching frequency range using FREQ mode 9 kΩ ≤ RFREQ≤ 99 kΩ 200 800 kHz
fSW Switching frequency RFREQ = 80.6 kΩ 228 253 278 kHz
RFREQ = 49.9 kΩ 360 400 440 kHz
FSSS Frequency span of spread spectrum operation ±6 %
EXTERNAL CLOCK(SYNC)
fFREQ/SYNC Switching frequency using external clock on FREQ/SYNC pin 200 800 kHz
TSYNC_MIN Minimum SYNC input pulse width fSYNC = 400kHz, VFREQ/SYNC > VIH_FREQ/SYNC, VFREQ/SYNC < VIL_FREQ/SYNC 100 ns
TLOCK_IN PLL lock time 100 µs
tDEGA_CC_ATT_DETM Attach asserting deglitch in the Detached Mode 1.29 2.05 3.05 ms
tDEGA_CC_DETACH_SINKM Detach asserting deglitch for exiting SINK Mode 8.2 12.5 18 ms
tDEGA_CC_SHORT Detach, Rd and Ra asserting deglitch 92 192 339 µs
tDEGA_CC_LONG Long deglitch 103 148 200 ms